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altera corporation section i?1 preliminary section i. cyclone ii device family data sheet this section provides informatio n for board layout designers to successfully layout their boards for cyclone ? ii devices. it contains the required pcb layout guidelines, device pin tables, and package specifications. this section includes the following chapters: chapter 1. introduction chapter 2. cyclone ii architecture chapter 3. configuration & testing chapter 4. hot socketing & power-on reset chapter 5. dc characteristic s & timing specifications chapter 6. reference & ordering information revision history the table below shows th e revision history for chapters 1 through 6 . chapter(s) date / version changes made 1 november 2005, v2.1 updated introduction and features. updated table 1?3 . july 2005, v2.0 updated technical content throughout. updated table 1?2 . added tables 1?3 and 1?4 . november 2004, v1.1 updated table 1?2 . updated bullet list in the ?features? section. june 2004 v1.0 added document to the cyclone ii device handbook.
section i?2 altera corporation preliminary cyclone ii device family data sheet cyclone ii device handbook, volume 1 2 november 2005, v2.1 updated table 2?8 . updated figures 2?11 and 2?12 . updated programmable drive strength table. updated table 2?17 . updated table 2?19 . updated table 2?20 . july 2005, v2.0 updated technical content throughout. updated table 2?17 . february 2005 v1.2 updated figure 2-12. november 2004, v1.1 updated table 2?20 . june 2004, v1.0 added document to the cyclone ii device handbook. 3 july 2005, v2.0 updated technical content. february 2005, v1.2 updated information on jtag chain limitations. november 2004. v1.1 updated table 3?4 . june 2004, v1.0 added document to the cyclone ii device handbook. 4 july 2005, v2.0 updated technical content throughout. february 2005 v1.1 removed esd section. june 2004, v1.0 added document to the cyclone ii device handbook. 5 march 2006, v2.3 updated table 5?15 and associated notes. december 2005, v2.2 updated pll timing specifications november 2005, v2.1 updated technical content throughout. july 2005, v2.0 updated technical content throughout. november 2004, v1.1 updated the ?differential i/o standards? section. updated table 5?51 . june 2004, v1.0 added document to the cyclone ii device handbook. chapter(s) date / version changes made
altera corporation 1?3 cyclone ii device handbook, volume 1 6 november 2005, v1.2 updated software introduction. november 2004, v1.1 updated figure 6?1 . june 2004, v1.0 added document to the cyclone ii device handbook. chapter(s) date / version changes made
1?4 altera corporation cyclone ii device handbook, volume 1 cyclone ii device family data sheet
altera corporation 1?1 november 2005 preliminary 1. introduction introduction following the immensel y successful first-generation cyclone ? device family, altera ? cyclone ii fpgas extend th e low-cost fpga density range to 68,416 logic elements (les ) and provide up to 622 usable i/o pins and up to 1.1 mbits of embedd ed memory. cyclone ii fpgas are manufactured on 300-mm wafers using tsmc's 90-nm low-k dielectric process to ensure rapid availability and low cost. by minimizing silicon area, cyclone ii devices can support complex digital systems on a single chip at a cost that rivals that of asics. unlike other fpga vendors who compromise power consumption and pe rformance for low-cost, altera's latest generation of low-cost fpgas ?cyclone ii fpgas, offer 60 percent higher performance and half the power consumption of competing 90-nm fpgas. the low cost and op timized feature set of cyclone ii fpgas make them ideal solutions for a wide array of automotive, consumer, communications, video processing, test and measurement, and other end-market solutions. reference designs, system diagrams, and ip, found at www.altera.com , are available to help you rapidly develop complete end-market solutions using cyclone ii fpgas. low-cost embedded processing solutions cyclone ii devices support the nios ii embedded processor which allows you to implement custom-fit embedded processing solutions. cyclone ii devices can also expand the peripheral set, memory, i/o, or performance of embedded processors. single or multiple nios ii embedded processors can be designed into a cyclone ii device to provide additional co-processing power or even replace existing embedded processors in your system. using cyclone ii and nios ii together allow for low-cost, high-performance embedded processi ng solutions which allow you to extend your product's life cycle and improve time to market over standard product solutions. low-cost dsp solutions use cyclone ii fpgas alone or as ds p co-processors to improve price-to- performance ratios for digital signal processing (dsp) applications. you can implement high-performance yet low-cost dsp systems with the following cyclone ii features and design support: up to 150 18 18 multipliers up to 1.1 mbit of on-chip embedded memory high-speed interfaces to external memory cii51001-2.1
1?2 altera corporation cyclone ii device handbook, volume 1 november 2005 features dsp intellectual property (ip) cores dsp builder interface to the ma thworks simulink and matlab design environment dsp development kit, cyclone ii edition cyclone ii devices include a powerful fpga feature set optimized for low-cost applications including a wide range of density, memory, embedded multiplier, and packaging op tions. cyclone ii devices support a wide range of common external me mory interfaces and i/o protocols required in low-cost applications. parameterizable ip cores from altera and partners make using cyclone ii interfaces and protocols fast and easy. features the cyclone ii device family offers the following features: high-density architecture with 4,608 to 68,416 les m4k embedded memory blocks up to 1.1 mbits of ram availabl e without reducing available logic 4,096 memory bits per block (4,6 08 bits per block including 512 parity bits) variable port configurations of 1, 2, 4, 8, 9, 16, 18, 32, and 36 true dual-port (one read and one write, two reads, or two writes) operation for 1, 2, 4, 8, 9, 16, and 18 modes byte enables for data input masking during writes up to 260-mhz operation embedded multipliers up to 150 18- 18-bit multipliers are each configurable as two independent 9- 9-bit multi pliers with up to 250-mhz performance optional input and output registers advanced i/o support high-speed differential i/o standard support, including lvds, rsds, mini-lvds, lvpecl, differential hstl, and differential sstl single-ended i/o standard suppo rt, including 2.5-v and 1.8-v, sstl class i and ii, 1. 8-v and 1.5-v hstl class i and ii, 3.3-v pci and pci-x 1.0, 3.3-, 2.5-, 1.8-, and 1.5-v lvcmos, and 3.3-, 2.5-, and 1.8-v lvttl peripheral component interconnect special interest group (pci sig) pci local bus specification, revision 3.0 compliance for 3.3-v operation at 33 or 66 mhz for 32- or 64-bit interfaces
altera corporation 1?3 november 2005 cyclone ii device handbook, volume 1 introduction pci express with an external ti phy and an altera pci express 1 megacore ? function 133-mhz pci-x 1.0 specification compatibility high-speed external memory support, including ddr, ddr2, and sdr sdram, and qdrii sr am supported by drop in altera ip megacore functions for ease of use three dedicated registers per i/o element (ioe): one input register, one output register, and one output-enable register programmable bus-hold feature programmable output drive strength feature programmable delays from the pin to the ioe or logic array i/o bank grouping for unique vccio and/or vref bank settings multivolt ? i/o standard support for 1.5-, 1.8-, 2.5-, and 3.3- interfaces hot-socketing operation support tri-state with weak pull-up on i/o pins before and during configuration programmable open-drain outputs series on-chip termination support flexible clock management circuitry hierarchical clock network fo r up to 402.5-mhz performance up to four plls per device pr ovide clock multiplication and division, phase shifting, programm able duty cycle, and external clock outputs, allowing system-level clock management and skew control up to 16 global clock lines in th e global clock network that drive throughout the entire device device configuration fast serial configuration allows configuration times less than 100 ms decompression feature allows for smaller programming file storage and faster configuration times supports multiple configuration mo des: active serial, passive serial, and jtag-based configuration supports configuration through lo w-cost serial configuration devices device configuration supports multi ple voltages (either 3.3, 2.5, or 1.8 v) intellectual property altera megafunction and altera megacore function support, and altera megafunctions partners program (ampp sm ) megafunction support, for a wide range of embedded processors, on-chip and off-c hip interfaces, peripheral
1?4 altera corporation cyclone ii device handbook, volume 1 november 2005 features functions, dsp functi ons, and communications functions and protocols. visit the altera ipmegastore at www.altera.com to download ip megacore functions. nios ii embedded processor support table 1?1 lists the cyclone ii device family features. table 1?2 lists the cyclone ii device package offerings and maximum user i/o pins. table 1?1. cyclone ii fpga family features feature ep2c5 ep2c8 ep2c20 ep2c35 ep2c50 ep2c70 les 4,608 8,256 18,752 33,216 50,528 68,416 m4k ram blocks (4 kbits plus 512 parity bits 26 36 52 105 129 250 total ram bits 119,808 165,888 239,616 483,840 594,432 1,152,000 embedded multipliers (1) 13 18 26 35 86 150 plls 224444 maximum user i/o pins 158 182 315 475 450 622 note to ta b l e 1 ? 1 : (1) this is the total number of 18 18 multipliers. for the total number of 9 9 multipliers per device, multiply the total number of 18 18 multipliers by 2.
altera corporation 1?5 november 2005 cyclone ii device handbook, volume 1 introduction cyclone ii devices support vertical migration within the same package (for example, you can migrate between the ep2c35, epc50, and ep2c70 devices in the 672-pin fineline bga pa ckage). the exception to vertical migration support within the cyclone ii family is noted in table 1?3 . table 1?2. cyclone ii package opti ons & maximum user i/o pins note (1) device 144-pin tqfp (2) 208-pin pqfp (3) 240-pin pqfp 256-pin fineline bga 484-pin fineline bga 484-pin ultra fineline bga 672-pin fineline bga 896-pin fineline bga ep2c5 (6) 89 142 158 (5) ep2c8 (6) 85 138 182 ep2c20 (6) 142 152 315 ep2c35 (6) 322 322 475 ep2c50 (6) 294 294 450 ep2c70 (6) 422 622 notes to ta b l e 1 ? 2 : (1) cyclone ii devices support vertical migration within the same package (for example, you can migrate between the ep2c20 device in the 484-pin fineline bga ? package and the ep2c35 and ep2c50 devices in the same package). (2) tqfp: thin quad flat pack. (3) pqfp: plastic quad flat pack. (4) this package offering is preliminary. (5) vertical migration is supported between the ep2c5f256 and the ep2c8f256 devices. however, not all of the dq and dqs groups are supported. vertical migration between the ep2c5 and the ep2c20 in the f256 package is not supported. (6) the i/o pin counts for the ep2c5 and ep2c8 devices include 8 dedicated clock pins that can be used for data inputs. the i/o counts for the ep2c20, ep2c35, ep2c50, and ep2c70 devices in clude 16 dedicated clock pins that can be used for data inputs.
1?6 altera corporation cyclone ii device handbook, volume 1 november 2005 features vertical migration means that yo u can migrate to devices whose dedicated pins, configur ation pins, and power pins are the same for a given package across device densities. 1 when moving from one density to a larger density, i/o pins are often lost because of the greater number of power and ground pins required to support the addi tional logic within the larger device. for i/o pin migration across densities, you must cross reference the available i/o pins us ing the device pin-outs for all planned densities of a given pack age type to identify which i/o pins are migratable. to ensure that your board layout supports migratable densities within one package offering, enable the ap plicable vertical migration path within the quartus ? ii software (go to assignments menu, then device, then click the migration devices button). after compilation, check the information messages for a full list of i/o, dq, lvds, and other pins that are not available because of the selected migration path. table 1?3 lists the cyclone ii device package offerings and shows the total number of non-migratable i/o pins when migrating from one density device to a larger density device. table 1?3. total number of non-migratable i/o pins for cyclone ii ver tical migration paths vertical migration path 144-pin tqfp 208-pin pqfp 256-pin fineline bga (1) 484-pin fineline bga (2) 484-pin ultra fineline bga 672-pin fineline bga (3) ep2c5 to ep2c8 441 (4) ep2c8 to ep2c20 30 ep2c20 to ep2c35 16 ep2c35 to ep2c50 28 (5) 28 ep2c50 to ep2c70 28 28 notes to ta b l e 1 ? 3 : (1) vertical migration between the ep2c5f256 and the ep2c20f256 devices is not supported. (2) when migrating from the ep2c20f484 device to the ep2c50 f484 device, a total of 39 i/o pins are non-migratable. (3) when migrating from the ep2c35f672 device to the ep2c70 f672 device, a total of 56 i/o pins are non-migratable. (4) in addition to the one non-migratable i/o pin, there are 34 dq pins that are non-migratable. (5) this package offering is preliminary. this inform ation will be available in a future version of the cyclone ii device handbook .
altera corporation 1?7 november 2005 cyclone ii device handbook, volume 1 introduction cyclone ii devices are available in up to three speed grades: -6, -7, and -8, with -6 being the fastest. table 1?4 shows the cyclone ii device speed-grade offerings. table 1?4. cyclone ii device speed grades device 144-pin tqfp 208-pin pqfp 240-pin pqfp 256-pin fineline bga 484-pin fineline bga 484-pin ultra fineline bga 672-pin fineline bga 896-pin fineline bga ep2c5 - 6, - 7, - 8 - 7, - 8 - 6, - 7, - 8 ep2c8 - 6, - 7, - 8 - 7, - 8 - 6, - 7, - 8 ep2c20 - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c35 - 6, - 7, - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c50 - 6, - 7, - 8 - 6, - 7, - 8 - 6, - 7, - 8 ep2c70 - 6, - 7, - 8 - 6, - 7, - 8
1?8 altera corporation cyclone ii device handbook, volume 1 november 2005 features
altera corporation 2?1 november 2005 preliminary 2. cyclone ii architecture functional description cyclone? ii devices contain a two-di mensional row- and column-based architecture to implement custom logi c. column and row interconnects of varying speeds provide signal interc onnects between logic array blocks (labs), embedded memory blocks, and embedded multipliers. the logic array consists of labs, wi th 16 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. cyclone ii devi ces range in density from 4,608 to 68,416 les. cyclone ii devices provide a global clock network and up to four phase- locked loops (plls). the gl obal clock network consists of up to 16 global clock lines that drive throughout th e entire device. the global clock network can provide clocks for all resources within the device, such as input/output elements (ioes), les, embedded multipliers, and embedded memory blocks. the global clock lines can also be used for other high fan-out signals. cyclon e ii plls provide general-purpose clocking with clock synthesis and ph ase shifting as well as external outputs for high-speed differential i/o support. m4k memory blocks are true dual-por t memory blocks wi th 4k bits of memory plus parity (4, 608 bits). these blocks provide dedicated true dual-port, simple dual-port, or sing le-port memory up to 36-bits wide at up to 260 mhz. these blocks are arra nged in columns across the device in between certain labs. cyclone ii devices offer between 119 to 1,152 kbits of embedded memory. each embedded multiplier block can im plement up to either two 9 9-bit multipliers, or one 18 18-bit multiplier with up to 250-mhz performance. embedded multipliers are arranged in columns across the device. each cyclone ii device i/o pin is fed by an ioe located at the ends of lab rows and columns around the peripher y of the device. i/o pins support various single-ended and differential i/o standards, such as the 66- and 33-mhz, 64- and 32-bit pci standard, pci-x, and the lvds i/o standard at a maximum data rate of 805 megabits per second (mbps) for inputs and 640 mbps for outputs. each ioe contains a bidirectional i/o buffer and three registers for registering input, output, and output-enable signals. dual-purpose dqs, dq, and dm pins along with delay chains (used to cii51002-2.1
2?2 altera corporation cyclone ii device handbook, volume 1 november 2005 functional description phase-align double data rate (ddr) si gnals) provide inte rface support for external memory devices such as ddr, ddr2, and single data rate (sdr) sdram, and qdrii sram devices at up to 167 mhz. figure 2?1 shows a diagram of the cyclone ii ep2c20 device. figure 2?1. cyclone ii ep2c20 device block diagram the number of m4k memory blocks, embedded multiplier blocks, plls, rows, and columns vary per device. table 2?1 lists the resources available in each cyclone ii device. pll pll ioes pll pll ioes ioes logic array logic array logic array logic array ioes m4k block s m4k blocks embedded multipliers table 2?1. cyclone ii device resources device lab columns lab rows les plls m4k memory blocks embedded multiplier blocks ep2c5 24 13 4,608 2 26 13 ep2c8 30 18 8,256 2 36 18 ep2c20 46 26 18,752 4 52 26 ep2c35 60 35 33,216 4 105 35 ep2c50 74 43 50,528 4 129 86 ep2c70 86 50 68,416 4 250 150
altera corporation 2?3 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture logic elements the smallest unit of logic in the cycl one ii architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le features: a four-input look-up table (lut), wh ich is a function generator that can implement any functi on of four variables a programmable register a carry chain connection a register chain connection the ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects support for register packing support for register feedback figure 2?2 shows a cyclone ii le. figure 2?2. cyclone ii le labclk1 labclk2 labclr2 lab carry-in clock & clock enable select lab carr y -out look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register clrn d q ena register bypass packed register select chip-wide reset (dev_clrn) labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear logic data1 data2 data3 data4 labclr1 local routing register chain output register feedback register chain routing from previous le
2?4 altera corporation cyclone ii device handbook, volume 1 november 2005 logic elements each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, clock, clock enable, and clear inputs. signals that use the glob al clock network, genera l-purpose i/o pins, or any internal logic can drive the register?s clock and clear control signals. either general-purpose i/o pins or internal logic can drive the clock enable. for combinational functions, the lut output bypasses the register and drives directly to the le outputs. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources, allowing the lut to drive one output while the register drives another output. this feature, register packing, improves device utilization because the device can use the register and the lut for unrelated functions. when using register packing, the lab-wide synchronous load control signal is not available. see ?lab control signals? on page 2?8 for more information. another special packing mode allows the register output to feed back into the lut of the same le so that the re gister is packed with its own fan-out lut, providing another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. in addition to the three general routing outputs, the les within an lab have register chain outputs. register chain outputs allow registers within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinational function and the registers to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local interconnect resources. see ?multitrack interconnect? on page 2?10 for more information on register chain connections. le operating modes the cyclone ii le operates in one of the following modes: normal mode arithmetic mode each mode uses le resources differently. in each mode, six available inputs to the le?the four data inputs from the lab local interconnect, the lab carry-in from the previous carry-chain lab, and the register chain connection?are directed to diff erent destinations to implement the desired logic function. lab-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes.
altera corporation 2?5 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture the quartus ? ii software, in conjunction with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinational functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?3 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. les in normal mode support packed registers and register feedback. figure 2?3. le in normal mode data1 four-input lut data2 data3 cin (from cout of previous le) data4 clock (lab wide) ena (lab wide) aclr (lab wide) clrn d q ena sclear (lab wide) sload (lab wide) register chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback packed register input
2?6 altera corporation cyclone ii device handbook, volume 1 november 2005 logic elements arithmetic mode the arithmetic mode is ideal for implementing adders, counters, accumulators, and co mparators. an le in arithmetic mode implements a 2-bit full adder and basic carry chain (see figure 2?4 ). les in arithmetic mode can drive out registered and unregistered versions of the lut output. register feedback and regist er packing are supported when les are used in arithmetic mode. figure 2?4. le in arithmetic mode the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 16 les by automatically linking labs in the same column. for enhanced fitting, a long carry chain runs vertically, whic h allows fast horizontal connections to m4k memory blocks or embedded multipliers through direct link interconnects. for example, if a desi gn has a long carry chain in a lab column next to a column of m4k memory blocks, any le output can feed an adjacent m4k memory block thro ugh the direct link interconnect. whereas if the carry chains ran ho rizontally, any lab not next to the column of m4k memory blocks would use other row or column interconnects to drive a m4k memory block. a carry chain continues as far as a full column. clock (lab wide) ena (lab wide) aclr (lab wide) clrn d q ena register chain connection sclear (lab wide) sload (lab wide) register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback three-input lut three-input lut cin (from cout of previous le) data2 data1 cout
altera corporation 2?7 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture logic array blocks each lab consists of the following: 16 les lab control signals le carry chains register chains local interconnect the local interconnect transfers sign als between les in the same lab. register chain connections transfer the output of one le?s register to the adjacent le?s register within an lab. the quartus ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, and register chain connections for performance and area efficiency. figure 2?5 shows the cyclone ii lab. figure 2?5. cyclone ii lab structure direct link interconnect from adjacen t block direct link interconnect to adjacent block row interconnect column interconnect local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block
2?8 altera corporation cyclone ii device handbook, volume 1 november 2005 logic array blocks lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. neighboring labs, plls, m4k ram blocks, and embedded multi pliers from the left and right can also drive an lab?s local interconnect through th e direct link connection. the direct link connection feature minimi zes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 48 les through fast local and direct link interconnects. figure 2?6 shows the direct link connection. figure 2?6. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include: two clocks two clock enables two asynchronous clears one synchron ous clear one synchronous load lab direct link interconnect to right direct link interconnect from right lab, m4k memory block, embedded multiplier, pll, or ioe output direct link interconnect from left lab, m4k memory block, embedded multiplier, pll, or ioe output local interconnect direct link interconnect to left
altera corporation 2?9 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture this gives a maximum of seven contro l signals at a time. when using the lab-wide synchronous load, the clkena of labclk1 is not available. additionally, register packing and synchronous load cannot be used simultaneously. each lab can have up to four non-glob al control signals. additional lab control signals can be used as lo ng as they are global signals. synchronous clear and load signals are useful for implementing counters and other functions. the synchronous clear and synchronous load signals are lab-wide signals that affe ct all registers in the lab. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal also uses labclkena1 . if the lab uses both the rising and falling ed ges of a clock, it also uses both lab-wide clock signals. de-asserting the clock enable signal turns off the lab-wide clock. the lab row clocks [5..0] and lab local interconnect generate the lab- wide control signals. the multitrack ? interconnect?s inherent low skew allows clock and control signal di stribution in addition to data. figure 2?7 shows the lab control signal generation circuit. figure 2?7. lab-wide control signals lab-wide signals control the logic for the register?s clear signal. the le directly supports an asynchronous clear function. each lab supports up to two asynchronous clear signals ( labclr1 and labclr2 ). labclkena1 labclk2 labclk1 labclkena2 labclr1 dedicated lab row clocks local interconnect local interconnect local interconnect local interconnect syncload synclr labclr2 6
2?10 altera corporation cyclone ii device handbook, volume 1 november 2005 multitrack interconnect a lab-wide asynchronous load signal to control the logic for the register?s preset signal is not availabl e. the register preset is achieved by using a not gate push-back technique. cyclone ii devices can only support either a preset or asynchronous clear signal. in addition to the clea r port, cyclone ii devices provide a chip-wide reset pin ( dev_clrn ) that resets all registers in th e device. an option set before compilation in the quartus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the cyclone ii architecture, conne ctions between les, m4k memory blocks, embedded multipliers, and device i/o pins are provided by the multitrack interconnect structure with directdrive? technology. the multitrack interconnect consists of continuous, performance-optimized routing lines of different speeds used for inter- and intra-design block connectivity. the quartus ii compiler automatically places critical paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row (direct link, r4, and r24) and column (register chain, c4, and c 16) interconnects that span fixed distances. a routing structure with fi xed-length resources for all devices allows predictable and repeatable performance when migrating through different device densities. row interconnects dedicated row interconnects route signals to and from labs, plls, m4k memory blocks, and embedded multipliers within the same row. these row resources include: direct link interconnects between labs and adjacent blocks r4 interconnects traversing fo ur blocks to the right or left r24 interconnects for high-speed ac cess across the length of the device
altera corporation 2?11 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture the direct link interconnect allows an lab, m4k memory block, or embedded multiplier block to drive into the local interconnect of its left and right neighbors. only one side of a pll block interfaces with direct link and row interconnects. the direct link interconnect provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four la bs, three labs and one m4k memory block, or three labs and one embedded multiplier to the right or left of a source lab. these resources are used for fast row connections in a four- lab region. every lab has its own set of r4 interconnects to drive either left or right. figure 2?8 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by labs, m4k memory blocks, embedded multipliers, plls, and row ioes. for lab interfacing, a primary lab or lab neighbor (see figure 2?8 ) can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. additionally, r4 interconnects can drive r24 interc onnects, c4, and c16 interconnects for connections from one row to another. figure 2?8. r4 interconnect connections notes to figure 2?8 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor
2?12 altera corporation cyclone ii device handbook, volume 1 november 2005 multitrack interconnect r24 row interconnects span 24 labs and provide the fastest resource for long row connections between non-ad jacent labs, m4k memory blocks, dedicated multipliers, and row ioes. r24 row interconnects drive to other row or column interconnects at every fourth lab. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects and do not drive directly to lab local interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. column interconnects the column interconnect operates similar to the row interconnect. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, m4k memory blocks, embedded multipliers, and row and column ioes. these column resources include: register chain intercon nects within an lab c4 interconnects traversing a distan ce of four blocks in an up and down direction c16 interconnects for high-speed vertical routing through the device cyclone ii devices include an enhanc ed interconnect structure within labs for routing le output to le input connections faster using register chain connections. the register chai n connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. th e quartus ii compiler automatically takes advantage of these resources to improve utilization and performance. figure 2?9 shows the register chain interconnects.
altera corporation 2?13 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?9. register chain interconnects the c4 interconnects span four labs, m4k blocks, or embedded multipliers up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?10 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture blocks, including plls, m4k memory blocks, embedded multiplier blocks, and column and row ioes. for lab interconnection, a primary lab or its lab neighbor (see figure 2?10 ) can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for colu mn-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 le 11 le 12 le13 le 14 le 15 le 16 carry chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab
2?14 altera corporation cyclone ii device handbook, volume 1 november 2005 multitrack interconnect figure 2?10. c4 inte rconnect connections note (1) note to figure 2?10 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect primary lab lab neighbor
altera corporation 2?15 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, m4k memory blocks, embedded multipliers, and ioes. c16 column interconnects drive to other row and column interconnects at every fourth lab. c16 column interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. c16 interconnects can drive r24, r4, c16, and c4 interconnects. device routing all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (fo r example, m4k memory, embedded multiplier, or pll) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link intercon nects for fast connections to and from a neighboring lab. table 2?2 shows the cyclone ii device?s routing scheme. table 2?2. cyclone ii device routing scheme (part 1 of 2) source destination register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect le m4k ram block embedded multiplier pll column ioe row ioe register chain v local interconnect vvvvvv direct link interconnect v r4 interconnect v vvvv r24 interconnect vvvv c4 interconnect v vvvv c16 interconnect vvvv
2?16 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops global clock network & phase-locked loops cyclone ii devices provide global clock networks and up to four plls for a complete clock management solution . cyclone ii clock network features include: up to 16 global clock networks up to four plls global clock network dynamic clock source selection global clock network dynamic enable and disable le vvvv v m4k memory block vvv v embedded multipliers vvv v pll vv v column ioe vv row ioe vvvv table 2?2. cyclone ii device routing scheme (part 2 of 2) source destination register chain local interconnect direct link interconnect r4 interconnect r24 interconnect c4 interconnect c16 interconnect le m4k ram block embedded multiplier pll column ioe row ioe
altera corporation 2?17 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture each global clock network has a cl ock control block to select from a number of input clock sources (pll clock outputs, clk[] pins, dpclk[] pins, and internal logic) to driv e onto the global clock network. table 2?3 lists how many plls, clk[] pins, dpclk[] pins, and global clock networks are available in each cyclone ii device. clk[] pins are dedicated clock pins and dpclk[] pins are dual-purpose clock pins. figures 2?11 and 2?12 show the location of the cyclone ii plls, clk[] inputs, dpclk[] pins, and clock control blocks. table 2?3. cyclone ii device clock resources device number of plls number of clk pins number of dpclk pins number of global clock networks ep2c5 2 8 8 8 ep2c8 2 8 8 8 ep2c20 4 16 20 16 ep2c35 4 16 20 16 ep2c50 4 16 20 16 ep2c70 4 16 20 16
2?18 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops figure 2?11. ep2c5 & ep2c8 pll, clk[], d pclk[] & clock control block locations note to figure 2?11 : (1) there are four clock control blocks on each side. pll 2 clk[7..4] dpclk7 dpclk6 clk[3..0] dpclk0 dpclk1 dpclk10 dpclk8 dpclk2 gclk[7..0] gclk[7..0] dpclk4 pll 1 8 8 8 8 clock control block (1) clock control block (1) 4 4 4 4
altera corporation 2?19 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?12. ep2c20 & larger pll, clk[], d pclk[] & clock control block locations notes to figure 2?12 : (1) there are four clock control blocks on each side. (2) only one of the corner cdpclk pins in each corner can feed the clock control block at a time. the other cdpclk pins can be used as general-purpose i/o pins. pll 4 pll 3 pll 2 clk[7..4] dpclk7 cdpclk5 cdpclk4 dpclk6 clk[3..0] dpclk0 cdpclk0 cdpclk1 dpclk1 cdpclk7 dpclk[9..8] dpclk[11..10] clk[11..8] gclk[15..0] gclk[15..0] pll 1 cdpclk6 cdpclk2 dpclk[5..4] dpclk[3..2] clk[15..12] cdpclk3 clock control block (1) clock control block (1) 16 16 16 16 22 4 4 4 4 4 2 2 4 (2) (2) (2) (2) 4 4 3 3 3 3
2?20 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops dedicated clock pins larger cyclone ii devices (ep2c20 and larger devices) have 16 dedicated clock pins ( clk[15..0] , four pins on each side of the device). smaller cyclone ii devices (ep2c5 and ep2c8 devices) have eight dedicated clock pins ( clk[7..0] , four pins on left and right sides of the device). these clk pins drive the global clock network (gclk), as shown in figures 2?11 and 2?12 . if the dedicated clock pins are not us ed to feed the glob al clock networks, they can be used as general-purpose input pins to feed the logic array using the multitrack interconnect. howe ver, if they are used as general- purpose input pins, they do not have support for an i/o register and must use le-based registers in place of an i/o register. dual-purpose clock pins cyclone ii devices have either 20 dual-purpose clock pins, dpclk[19..0] or 8 dual-purpose clock pins, dpclk[7..0] . in the larger cyclone ii devices (ep2c20 devices and higher), there are 20 dpclk pins; four on the left and right sides and six on the top and bottom of the device. the corner cdpclk pins are first multiplexed before they drive into the clock control bloc k. since the signals pass through a multiplexer before feeding the clock control block, these signals incur more delay to the clock control block than other dpclk pins that directly feed the clock control block. in the smaller cyclone ii devices (ep2c5 and ep2c8 devices), there are eight dpclk pins; two on each side of the device (see figures 2?11 and 2?12 ). a programmable delay chain is available from the dpclk pin to its fan- out destinations. to set the propagation delay from the dpclk pin to its fan-out destinations, use the input delay from dual-purpose clock pin to fan-out destinations assignment in the quartus ii software. these dual-purpose pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables, or protocol control signals such as trdy and irdy for pci, or dqs signals for ex ternal memory interfaces.
altera corporation 2?21 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture global clock network the 16 or 8 global clock networks drive throughout the entire device. dedicated clock pins ( clk[] ), pll outputs, the logic array, and dual- purpose clock ( dpclk[] ) pins can also drive the global clock network. the global clock network can provide clocks for all resources within the device, such as ioes, les, memory blocks, and embedded multipliers. the global clock lines can also be used for control signals, such as clock enables and synchronous or asynchrono us clears fed from the external pin, or dqs signals for ddr sdram or qdrii sram interfaces. internal logic can also drive the global cloc k network for internally generated global clocks and asynchronous clea rs, clock enables, or other control signals with large fan-out. clock control block there is a clock control block for each global clock netw ork available in cyclone ii devices. the clock control blocks are arranged on the device periphery and there are a maximum of 16 clock control blocks available per cyclone ii device. the larger cyclone ii devices (ep2c20 devices and larger) have 16 clock control blocks, four on each side of the device. the smaller cyclone ii devices (ep2c5 and ep2c8 devices) have eight clock control blocks, four on the left and right sides of the device. the control block has these functions: dynamic global clock network clock source selection dynamic enable/disable of the global clock network in cyclone ii devices, the dedicated clk[] pins, pll counter outputs, dpclk[] pins, and internal logic can all feed the clock control block. the output from the clock control block in turn feeds the corresponding global clock network. the following sources can be inputs to a given clock control block: four clock pins on the same si de as the clock control block three pll clock outputs from a pll four dpclk pins (including cdpclk pins) on the same side as the clock control block four internally-generated signals
2?22 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops of the sources listed, only two cloc k pins, two pll clock outputs, one dpclk pin, and one internally-generated signal are chosen to drive into a clock control block. figure 2?13 shows a more detailed diagram of the clock control block. out of these six inputs, the two clock input pins and two pll outputs can be dynamic select ed to feed a global clock network. the clock control block supports static selection of dpclk and the signal from internal logic. figure 2?13. clock control block notes to figure 2?13 : (1) the clkswitch signal can either be set through the configuration file or it can be dynamically set when using the manual pll switchover feature. the output of the multiplexer is the input reference clock (f in ) for the pll. (2) the clkselect[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for the global clock network when the device is in user mode. (3) the static clock select signals are se t in the configuration file and cannot be dynamically controlled when the device is in user mode. (4) internal logic can be used to enabled or di sabled the global clock network in user mode. clkswitch (1) static clock select (3) static clock select (3) internal logic clock control block dpclk or cdpclk clkselect[1..0] (2) clkena (4) inclk1 inclk0 clk[ n + 3] clk[ n + 2] clk[ n + 1] clk[ n ] f in c0 c1 c2 pll global clock enable/ disable (3)
altera corporation 2?23 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture global clock network distribution cyclone ii devices contains 16 global clock networks. the device uses multiplexers with these cl ocks to form six-bit buses to drive column ioe clocks, lab row clocks, or row ioe clocks (see figure 2?14 ). another multiplexer at the lab level selects tw o of the six lab row clocks to feed the le registers within the lab. figure 2?14. global clock network multiplexers lab row clocks can feed les, m4k memory blocks, and embedded multipliers. the lab row clocks also extend to the row i/o clock regions. ioe clocks are associated with row or column bl ock regions. only six global clock resources feed to these row and column regions. figure 2?15 shows the i/o clock regions. clock [15 or 7..0] row i/o region io_clk [5..0] column i/o region io_clk [5..0] lab row clock labclk[5..0] global clock network
2?24 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops figure 2?15. lab & i/o clock regions f for more information on the global clock network and the clock control block, see the plls in cyclone ii devices chapter in volume 1 of the cyclone ii devi ce handbook . column i/o clock region io_clk[5..0] column i/o clock region io_clk[5..0] 6 6 i/o clock regions i/o clock regions 8 or 16 global clock network row i/o cloc k region io_clk[5..0] cyclone logic array 6 6 lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] lab row clocks labclk[5..0] 6 6 6 6 6 6 6 6 6 6
altera corporation 2?25 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture plls cyclone ii plls provide general-purpos e clocking as well as support for the following features: clock multiplication and division phase shifting programmable duty cycle up to three internal clock outputs one dedicated external clock output clock outputs for differential i/o support manual clock switchover gated lock signal three different clock feedback modes control signals cyclone ii devices contain either two or four plls. table 2?4 shows the plls available for each cyclone ii device. table 2?4. cyclone ii device pll availability device pll1 pll2 pll3 pll4 ep2c5 vv ep2c8 vv ep2c20 vvvv ep2c35 vvvv ep2c50 vvvv ep2c70 vvvv
2?26 altera corporation cyclone ii device handbook, volume 1 november 2005 global clock network & phase-locked loops table 2?5 describes the pll features in cyclone ii devices. table 2?5. cyclone ii pll features feature description clock multiplication and division m / ( n post-scale counter) m and post-scale counter values (c0 to c2) range from 1 to 32. n ranges from 1 to 4. phase shift cyclone ii plls have an advan ced clock shift capability that enables programmable phase shifts in increments of at least 45. the finest resolution of phase shifting is determi ned by the voltage control oscillator (vco) period divided by 8 (for example, 1/1000 mhz/8 = down to 125-ps increments). programmable duty cycle the programmable duty cycl e allows plls to generate clock outputs with a variable duty cycle. this feature is supported on each pll post-scale counter (c0-c2). number of internal clock outputs the cyclone ii pll has three outputs which can drive the global clock network. one of these outputs (c2) can also drive a dedicated pll < # > _out pin (single ended or differential). number of external clock outputs the c2 output drives a dedicated pll < # > _out pin. if the c2 output is not used to drive an external clock output, it can be used to drive the internal global clock network. the c2 output can concurrently drive the external clock output and internal global clock network. manual clock switchover the cyclone ii plls suppor t manual switchover of the reference clock through internal logic. this enables you to switch between two reference input clocks during user mode for appl ications that may require clock redundancy or support for clocks with two different frequencies. gated lock signal the lock output indicates that there is a stable clock output signal in phase with the reference clock. cyclone ii plls include a programmable counter that holds the lock signal low for a user-selected number of input clock transitions, allowing the pll to lock before enabling the locked signal. either a gated locked signal or an ungated locked signal from the locked port can drive internal logic or an output pin. clock feedback modes in zero delay buffer mode , the external clock output pin is phase-aligned with the clock input pin for zero delay. in normal mode, the pll compensates for the internal global clock network delay from the input clock pin to the clock port of the ioe output registers or registers in the logic array. in no compensation mode, the pll does not compensate for any clock networks. control signals the pllenable signal enables and disables the plls. the areset signal resets/resynchronizes the inputs for each pll. the pfdena signal controls the phase frequency detector (pfd) output with a programmable gate.
altera corporation 2?27 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?16 shows a block diagram of the cyclone ii pll. figure 2?16. cyclone ii pll note (1) notes to figure 2?16 : (1) this input can be single-ended or differential. if you are using a differential i/o standard, then two clk pins are used. lvds input is supported via the secondary function of the dedicated clk pins. for example, the clk0 pin?s secondary function is lvdsclk1p and the clk1 pin?s secondary function is lvdsclk1n . if a differential i/o standard is assigned to the pll clock input pin, the corresponding clk(n) pin is also completely used. the figure 2?16 shows the possible clock input connections ( clk0 / clk1 ) to pll1. (2) this counter output is shared between a dedicated external clock output i/o and the global clock network. f for more information on cyclone ii plls, see the plls in the cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . embedded memory the cyclone ii embedded memory cons ists of columns of m4k memory blocks. the m4k memory bl ocks include input regi sters that synchronize writes and output registers to pipeline designs and improve system performance. the output registers can be bypassed, but input registers cannot. pfd loop filter lock detect & filter vco charge pump c0 c1 c2 m n global clock global clock global clock to i/o or general routing pll< # >_out post-scale counters vco phase selection selectable at each pll output port clk1 clk3 clk2 (1) clk0 (1) inclk0 inclk1 up down 8 8 8 f vco f fb f in reference input clock f ref = f in / n (2) manual clock switchover select signal k (3)
2?28 altera corporation cyclone ii device handbook, volume 1 november 2005 embedded memory each m4k block can implement various types of memory with or without parity, including true dual-port, simp le dual-port, and single-port ram, rom, and first-in first-out (fifo) buffers. the m4k blocks support the following features: 4,608 ram bits 250-mhz performance true dual-port memory simple dual-port memory single-port memory byte enable parity bits shift register fifo buffer rom various clock modes address clock enable 1 violating the setup or hold time on the memory block address registers could corrupt memory contents. this applies to both read and write operations. table 2?6 shows the capacity and distribut ion of the m4k memory blocks in each cyclone ii device. table 2?6. m4k memory capacity & distribution in cyclone ii devices device m4k columns m4k blocks total ram bits ep2c5 2 26 119,808 ep2c8 2 36 165,888 ep2c20 2 52 239,616 ep2c35 3 105 483,840 ep2c50 3 129 594,432 ep2c70 5 250 1,152,000
altera corporation 2?29 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture table 2?7 summarizes the features supported by the m4k memory. table 2?7. m4k memory features feature description maximum performance (1) 250 mhz total ram bits per m4k block (including parity bits) 4,608 configurations supported 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 (not available in true dual-port mode) 128 36 (not available in true dual-port mode) parity bits one parity bit for each byte. the parity bit, along with internal user logic, can implement parity checking for error detection to ensure data integrity. byte enable m4k blocks support byte writes when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. the byte enables allow the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. packed mode two single-port memory blocks can be packed into a single m4k block if each of the two independent block sizes are equal to or less than half of the m4k block size, and each of the single -port memory blocks is configured in si ngle-clock mode. address clock enable m4k blocks s upport address clock enable, which is used to hold the previous addr ess value for as long as the signal is enabled. this f eature is useful in handling misses in cache applications. memory initialization file ( .mif ) when configured as ram or rom, you can use an initialization file to pre-load the memory contents. power-up condition outputs cleared register clears out put registers only same-port read-during-write new dat a available at positive clock edge mixed-port read-during-wr ite old data available at positive clock edge note to ta b l e 2 ? 7 : (1) maximum performance information is pr eliminary until device characterization.
2?30 altera corporation cyclone ii device handbook, volume 1 november 2005 embedded memory clear signals when applied to input registers, the asynchronous clear signal for the trimatrix ? embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. memory modes table 2?8 summarizes the different memory modes supported by the m4k memory blocks. 1 embedded memory can be inferred in your hdl code or directly instantiated in the quartus ii software using the megawizard ? plug-in manager memory compiler feature. table 2?8. m4k memory modes memory mode description single-port memory m4k blocks suppo rt single-port mode, used when simultaneous reads and writes are not required. single-port memory supports non-simultaneous reads and writes. simple dual-port memory simple dual-port memory supports a simultaneous read and write. simple dual-port with mixed width simple dual-port memory mode with different read and write port widths. true dual-port memory true dual-port mode supports any combination of two-port operations: two r eads, two writes, or one read and one write at two different clock frequencies. true dual-port with mixed width true dual-port mode with different read and write port widths. embedded shift register m4k memory bloc ks are used to implement shift registers. data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. rom the m4k memory blocks support rom mode. a mif initializes the rom contents of these blocks. fifo buffers a single clock or dual clock fifo may be implemented in the m4k blocks. simultaneous read and write from an empty fifo buffer is not supported.
altera corporation 2?31 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture clock modes table 2?9 summarizes the different cloc k modes supported by the m4k memory. table 2?10 shows which clock modes are supported by all m4k blocks when configured in the different memory modes. m4k routing interface the r4, c4, and direct link interconnects from adjacent labs drive the m4k block local interconnect. the m4k blocks can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link input connections to the m4k block are possible from the left adjacent lab and another 16 possible from the right adjacent lab. m4k block outputs can also connect to left and right labs through each 16 direct link interconnects. figure 2?17 shows the m4k block to logic array interface. table 2?9. m4k clock modes clock mode description independent in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all regi sters on the port b side. input/output on each of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock controls the block?s data output registers. read/write up to two clocks are available in this mode. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . single in this mode, a single clock, together with clock enable, is used to control all registers of the memory block. asynchronous clear signals for the registers are not supported. table 2?10. cyclone ii m4k memory clock modes clocking modes true dual-port mode simple dual-port mode single-port mode independent v input/output vvv read/write v single clock vvv
2?32 altera corporation cyclone ii device handbook, volume 1 november 2005 embedded multipliers figure 2?17. m4k ram block lab row interface f for more information on cyclone ii embedded memory, see the cyclone ii memory blocks chapter in volume 1 of the cyclone ii device handbook . embedded multipliers cyclone ii devices have embedded multiplier blocks optimized for multiplier-intensive digital signal pr ocessing (dsp) func tions, such as finite impulse response (fir) filt ers, fast fourier transform (fft) functions, and discrete cosine transf orm (dct) functions. you can use the embedded multiplier in one of two basic operational modes, depending on the application needs: one 18-bit multiplier up to two independent 9-bit multipliers dataout m4k ram block datain address 16 16 16 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 interconnects r4 interconnects lab row clocks clocks byte enable control signals 6
altera corporation 2?33 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture embedded multipliers can operate at up to 250 mhz (for the fastest speed grade) for 18 18 and 9 9 multiplic ations when using both input and output registers. each cyclone ii device has one to three columns of embedded multipliers that efficiently implement multipli cation functions. an embedded multiplier spans the height of one lab row. table 2?11 shows the number of embedded multipliers in each cyclone ii device and the multipliers that can be implemented. the embedded multiplier consis ts of the following elements: multiplier block input and output registers input and output interfaces figure 2?18 shows the multiplier block architecture. table 2?11. number of embedded mult ipliers in cyclone ii devices note (1) device embedded multiplier columns embedded multipliers 9 9 multipliers 18 18 multipliers ep2c5 1 13 26 13 ep2c8 1 18 36 18 ep2c20 1 26 52 26 ep2c35 1 35 70 35 ep2c50 2 86 172 86 ep2c70 3 150 300 150 note to ta b l e 2 ? 11 : (1) each device has either the number of 9 9-, or 18 18-bit multipliers shown . the total number of multipliers for each device is not the sum of all the multipliers.
2?34 altera corporation cyclone ii device handbook, volume 1 november 2005 embedded multipliers figure 2?18. multiplier block architecture note to figure 2?18 : (1) if necessary, these signals can be registered once to match the data signal path. each multiplier operand can be a un ique signed or unsigned number. two signals, signa and signb , control the representation of each operand respectively. a logic 1 value on the signa signal indicates that data a is a signed number while a logic 0 value indicates an unsigned number. table 2?12 shows the sign of the mul tiplication result for the various operand sign repres entations. the result of the multiplication is signed if any one of the operands is a signed value. clrn dq ena data a data b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena data out embedded multiplier block output register input register table 2?12. multiplier sign representation data a (signa value) data b (signb value) result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed
altera corporation 2?35 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture there is only one signa and one signb signal for each dedicated multiplier. therefore, all of the data a inputs feeding the same dedicated multiplier must have the same sign re presentation. similarly, all of the data b inputs feeding the same dedicated multiplier must have the same sign representation. the signa and signb signals can be changed dynamically to modify the sign repres entation of the in put operands at run time. the multiplier offers full precision regardless of the sign representation and can be registered using dedicated registers located at the input register stage. multiplier modes table 2?13 summarizes the different modes that the embedded multipliers can operate in. table 2?13. embedded multiplier modes multiplier mode description 18-bit multiplier an embedded multiplier can be configured to support a single 18 18 multiplier for operand widths up to 18 bits. all 18-bit multiplier inputs and results can be registered independently. the multiplier operands can accept signed integers, unsigned integers, or a combination of both. 9-bit multiplier an embedded multipli er can be configured to support two 9 9 independent multipliers for operand widths up to 9-bits. both 9-bit multiplier inputs and results can be registered independently. the multiplier operands can accept signed integers, unsigned integers or a combination of both. there is only one signa signal to control the sign representation of both data a inputs and one signb signal to control the sign representation of both data b inputs of the 9-bit multipliers within the same dedicated multiplier.
2?36 altera corporation cyclone ii device handbook, volume 1 november 2005 embedded multipliers embedded multiplier routing interface the r4, c4, and direct link interconnects from adjacent labs drive the embedded multiplier row interface interconnect. the embedded multipliers can communicate with labs on either the left or right side through these row resources or with lab columns on either the right or left with the column resources. up to 16 direct link input connections to the embedded multiplier are possible from the left adjacent labs and another 16 possible from the right adjacent lab. embedded multiplier outputs can also connect to left and right labs through 18 direct link interconnects each. figure 2?19 shows the embedded multiplier to logic array interface. figure 2?19. embedded multiplier lab row interface lab lab row interface block embedded multiplier 16 [35..0] [35..0] embedded multiplier to lab row interface block interconnect region 36 inputs per row 36 outputs per row r4 interconnects c4 interconnects c4 interconnects direct link interconnect from adjacent lab 18 direct link outputs to adjacent labs direct link interconnect from adjacent lab 18 18 36 36 control 5 18 18 16 lab block interconect region lab block interconect region
altera corporation 2?37 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture there are five dynamic control inpu t signals that feed the embedded multiplier: signa , signb , clk , clkena , and aclr . signa and signb can be registered to match the data signal input path. the same clk , clkena , and aclr signals feed all registers within a single embedded multiplier. f for more information on cyclone ii embedded multipliers, see the embedded multipliers in cyclone ii devices chapter. i/o structure & features ioes support many features, including: differential and single-ended i/o standards 3.3-v, 64- and 32-bit, 66- and 33-mhz pci compliance joint test action group (jtag) boundary-scan test (bst) support output drive strength control weak pull-up resistors during configuration tri-state buffers bus-hold circuitry programmable pull-up resistors in user mode programmable input and output delays open-drain outputs dq and dqs i/o pins v ref pins cyclone ii device ioes contain a bidirectional i/o buffer and three registers for complete embedded bidirectional single data rate transfer. figure 2?20 shows the cyclone ii ioe structure. the ioe contains one input register, one output register, and one output enable register. you can use the input registers for fast setup times and output registers for fast clock-to-output times. additionally, you can use the output enable (oe) register for fast clock-to-output enable timing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. you ca n use ioes as input, output, or bidirectional pins.
2?38 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?20. cyclone ii ioe structure note to figure 2?20 : (1) there are two paths available for combinational or registered inputs to the logic array. each path contains a unique programmable delay chain. the ioes are located in i/o blocks ar ound the periphery of the cyclone ii device. there are up to five ioes per row i/o block and up to four ioes per column i/o block (column i/o blocks span two columns). the row i/o blocks drive row, column (only c4 interconnects), or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?21 shows how a row i/o block connects to the logic array. figure 2?22 shows how a column i/o bloc k connects to th e logic array. output register output input (1) oe register oe input register logic array
altera corporation 2?39 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?21. row i/o block c onnection to the interconnect notes to figure 2?21 : (1) the 35 data and control signals consist of five data out lines, io_dataout[4..0] , five output enables, io_coe[4..0] , five input clock enables, io_cce_in[4..0] , five output clock enables, io_cce_out[4..0] , five clocks, io_cclk[4..0] , five asynchronous clear signals, io_caclr[4..0] , and five synchronous clear signals, io_csclr[4..0] . (2) each of the five ioes in the row i/o block can have two io_datain (combinational or registered) inputs. 35 r4 & r24 interconnects c4 interconnects i/o block local interconnect 35 data and control signals from logic array (1 ) io_datain0[4..0] io_datain1[4..0] (2) io_clk[5..0] row i/o block contains up to five ioes direct link interconnect to adjacent lab direct link interconnect from adjacent lab lab local interconnect lab row i/o block
2?40 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?22. column i/o block connection to the interconnect notes to figure 2?22 : (1) the 28 data and control signals consist of four data out lines, io_dataout[3..0] , four output enables, io_coe[3..0] , four input clock enables, io_cce_in[3..0] , four output clock enables, io_cce_out[3..0] , four clocks, io_cclk[3..0] , four asynchronous clear signals, io_caclr[3..0] , and four synchronous clear signals, io_csclr[3..0] . (2) each of the four ioes in the column i/o block can have two io_datain (combinational or registered) inputs. 28 data & control signals from logic array (1) column i/o block contains up to four ioe s i/o block local interconnect io_datain0[3..0] io_datain1[3..0] (2) r4 & r24 interconnects lab local interconnect c4 & c24 interconnects 28 lab lab lab io_clk[5..0] column i/o block
altera corporation 2?41 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture the pin?s datain signals can drive the logic array. the logic array drives the control and data signals, providing a flexible routing resource. the row or column ioe clocks, io_clk[5..0] , provide a dedicated routing resource for low-skew, high-speed clocks. the global clock network generates the ioe clocks that feed the row or column i/o regions (see ?global clock network & phase-locked loops? on page 2?16 ). figure 2?23 illustrates the signal pa ths through the i/o block. figure 2?23. signal path through the i/o block each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr / preset , sclr / preset , clk_in , and clk_out . figure 2?24 illustrates the control signal selection. row or column io_clk[5..0] io_datain0 io_datain1 io_dataout io_coe oe ce_in ce_out io_cce_in aclr/preset io_cce_out sclr/preset io_caclr clk_in io_cclk clk_out dataout data and control signal selection ioe to logic array from logic array to other ioes io_csclr
2?42 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?24. control signal selection per ioe in normal bidirectional operation, you can use the input register for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. you can use the output register for data requiring fast clock-to-output performance. the oe register is available for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from the lo cal interconnect in the associated lab, dedicated i/o clocks, or the column and row interconnects. all registers share sclr and aclr , but each register can individually disable sclr and aclr . figure 2?25 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset dedicated i/o clock [5..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_caclr local interconnect io_csclr io_cce_out io_cce_in io_cclk
altera corporation 2?43 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?25. cyclone ii ioe in bidi rectional i/o configuration the cyclone ii device ioe includes programmable delays to ensure zero hold times, minimi ze setup times, or increa se clock to output times. a path in which a pin directly drives a register may require a programmable delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. programmable delays decrea se input-pin-to-logic-array and ioe input register delays. the quartus ii compiler can program these delays to automatically minimize setup time while providing a zero hold time. chip-wide reset oe register v ccio optional pci clamp column or row interconect io_clk[5..0] input register input pin to input register delay or input pin to logic array delay drive strength control open-drain output slew control sclr/preset oe clkout ce_out aclr/prn clkin ce_in output pin delay programmable pull-up resistor bus hold prn clrn dq output register prn clrn dq prn clrn dq v ccio data_in0 data_in1 ena ena ena
2?44 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features programmable delays can increase the register-to-pin delays for output registers. table 2?14 shows the programmable delays for cyclone ii devices. there are two paths in the ioe for an input to reach the logic array. each of the two paths can have a different delay. this allows you to adjust delays from the pin to internal le re gisters that reside in two different areas of the device. you set the two combinational input delays by selecting different delays for two different paths under the input delay from pin to internal cells logic option in the quartus ii software. however, if the pin uses the input register, one of delays is disregarded because the ioe only has two paths to in ternal logic. if the input register is used, the ioe uses one input path. the other input path is then available for the combinational path, and only one input delay assignment is applied. the ioe registers in each i/o block share the same source for clear or preset. you can program preset or clear for each individual ioe, but both features cannot be used simultaneously. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature pr events the inadvertent activation of another device?s active-low input upon power up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally a synchronous reset signal is availabl e for the ioe registers. external memory interfacing cyclone ii devices support a broad rang e of external memory interfaces such as sdr sdram, ddr sdram, ddr2 sdram, and qdrii sram external memories. cyclone ii devices feature dedicated high-speed interfaces that transfer data between external memory devices at up to 167 mhz/333 mbps for ddr and ddr2 sdram devices and 167 mhz/667 mbps for qdrii sram devices. the programmable dqs delay chain allows you to fi ne tune the phase shift for the input clocks or strobes to properly align clock edges as needed to capture data. table 2?14. cyclone ii progr ammable delay chain programmable delays quartus ii logic option input pin to logic array delay input delay from pin to internal cells input pin to input register delay input delay from pin to input register output pin delay delay from output register to output pin
altera corporation 2?45 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture in cyclone ii devices, all the i/o banks support sdr and ddr sdram memory up to 167 mhz/333 mbps. all i/o banks support dqs signals with the dq bus modes of 8/9, or 16/18. table 2?15 shows the external memory interfaces su pported in cyclone ii devices. cyclone ii devices use data (dq), data strobe (dqs), and clock pins to interface with ex ternal memory. figure 2?26 shows the dq and dqs pins in the 8/9 mode. table 2?15. external memory support in cyclone ii devices note (1) memory standard i/o standard maximum bus width maximum clock rate supported (mhz) maximum data rate supported (mbps) sdr sdram lvttl (2) 72 167 167 ddr sdram sstl-2 class i (2) 72 167 333 (1) sstl-2 class ii (2) 72 133 267 (1) ddr2 sdram sstl-18 class i (2) 72 167 333 (1) sstl-18 class ii (3) 72 125 250 (1) qdrii sram (4) 1.8-v hstl class i (2) 36 167 668 (1) 1.8-v hstl class ii (3) 36 100 400 (1) notes to table 2?15 : (1) the data rate is for designs using the clock delay control circuitry. (2) the i/o standards are supported on al l the i/o banks of the cyclone ii device. (3) the i/o standards are supported only on the i/o ba nks on the top and bottom of the cyclone ii device. (4) for maximum performance, altera recommends using the 1.8-v hstl i/o standard be cause of higher i/o drive strength. qdrii sram devices also su pport the 1.5-v hstl i/o standard.
2?46 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?26. cyclone ii device dq & dqs groups in 8/9 mode notes (1) , (2) notes to figure 2?26 : (1) each dq group consists of a dqs pin, dm pin, and up to nine dq pins. (2) this is an idealized pin layout. for actual pin layout, refer to the pin table. cyclone ii devices support the data strobe or read clock signal (dqs) used in ddr and ddr2 sdram. cy clone ii devices can use either bidirectional data strobes or unidirectional read clocks. the dedicated external memory interface in cyclone ii devices also includes programmable delay circuitry that ca n shift the incoming dqs signals to center align the dqs signals within the data window. the dqs signal is usually associated with a group of data (dq) pins. the phase-shifted dqs signals drive the gl obal clock network, which is used to clock the dq signals on internal le registers. table 2?16 shows the number of dq pin groups per device. dq pins dqs pin dm pin dq pins (2) table 2?16. cyclone ii dqs & dq bus mode support (part 1 of 2) note (1) device package number of 8 groups number of 9 groups (5) , (6) number of 16 groups number of 18 groups (5) , (6) ep2c5 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 433 ep2c8 144-pin tqfp (2) 3 300 208-pin pqfp 7 (3) 433 256-pin fineline bga ? 8 (3) 444 ep2c20 256-pin fineline bga 8 4 4 4 484-pin fineline bga 16 (4) 888 ep2c35 484-pin fineline bga 16 (4) 888 672-pin fineline bga 20 (4) 888
altera corporation 2?47 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture you can use any of the dq pins for th e parity pins in cyclone ii devices. the cyclone ii device family supports parity in the 8/9, and 16/18 mode. there is one parity bit available per eight bits of data pins. the data mask, dm, pins are requir ed when writing to ddr sdram and ddr2 sdram devices. a low signal on the dm pin indicates that the write is valid. if the dm signal is high, the memory masks the dq signals. in cyclone ii devices, the dm pins are assigned and are the preferred pins. each group of dqs and dq signals requires a dm pin. when using the cyclone ii i/o banks to interface with the ddr memory, at least one pll with tw o clock outputs is needed to generate the system and write clock. the system clock is used to clock the dq s write signals, commands, and addresses. the write clock is shifted by ?90 from the system clock and is used to cloc k the dq signals during writes. figure 2?27 illustrates ddr sdram interfacing from the i/o through the dedicated circuitry to the logic array. ep2c50 484-pin fineline bga 16 (4) 888 672-pin fineline bga 20 (4) 888 ep2c70 672-pin fineline bga 20 (4) 888 896-pin fineline bga 20 (4) 888 notes to table 2?16 : (1) numbers are preliminary. (2) ep2c5 and ep2c8 devices in the 144-pin tqfp package do not have any dq pin groups in i/o bank 1. (3) because of available clock resources, only a total of 6 dq/dqs grou ps can be implemented. (4) because of available clock resources, only a total of 14 dq/dqs groups can be implemented. (5) the 9 dqs/dq groups are also used as 8 dqs/dq groups. the 18 dqs/dq groups are also used as 16 dqs/dq groups. (6) for qdri implementation, if you connect the d ports (wri te data) to the cyclone ii dq pins, the total available 9 dqs /dq and 18 dqs/dq groups are half of that shown in table 2?16 . table 2?16. cyclone ii dqs & dq bus mode support (part 2 of 2) note (1) device package number of 8 groups number of 9 groups (5) , (6) number of 16 groups number of 18 groups (5) , (6)
2?48 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?27. ddr sdram interfacing f for more information on cyclone ii ex ternal memory interfaces, see the external memo ry interfaces chapter in volume 1 of the cyclone ii device handbook . dqs oe v cc pll gnd clk dq oe dataa datab resynchronizing to system clock global clock clock delay control circuitry -90? shifted clk adjacent lab les clock control block le register le register le register le register t en/dis dynamic enable/disable circuitry enout ena_register_mode le register le register le register le register le register le register le register le register le register
altera corporation 2?49 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture programmable drive strength the output buffer for each cyclone ii device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl, lvcmos, sstl-2 class i and ii, ss tl-18 class i and ii, hstl -18 class i and ii, and hstl-1.5 class i and ii standards have several levels of drive strength that you can control. using minimum settings provides signal slew rate control to reduce system no ise and signal overshoot. table 2?17 shows the possible settings for the i/o stan dards with drive strength control. table 2?17. programmable drive strength (part 1 of 2) note (1) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins lvttl (3.3 v) 4 4 88 12 12 16 16 20 20 24 24 lvcmos (3.3 v) 4 4 88 12 12 16 20 24 lvttl/lvcmos (2.5 v) 4 4 88 12 16 lvttl/lvcmos (1.8 v) 2 2 44 66 88 10 10 12 12
2?50 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features lvcmos (1.5 v) 2 2 44 66 8 sstl-2 class i 8 8 12 12 sstl-2 class ii 16 16 20 24 sstl-18 class i 6 6 88 10 10 12 sstl-18 class ii 16 18 hstl-18 class i 8 8 10 10 12 12 hstl-18 class ii 16 18 20 hstl-15 class i 8 8 10 12 hstl-15 class ii 16 note to table 2?17 : (1) the default current in the quartus ii software is the maximum setting for each i/o standard. table 2?17. programmable drive strength (part 2 of 2) note (1) i/o standard i oh /i ol current strength setting (ma) top & bottom i/o pins side i/o pins
altera corporation 2?51 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture open-drain output cyclone ii devices provide an option al open-drain (equivalent to an open-collector) output for each i/o pi n. this open-drain output enables the device to provide system-level co ntrol signals (that is, interrupt and write-enable signals) that can be asserted by any of several devices. slew rate control slew rate control is performed by using programmable output drive strength. bus hold each cyclone ii device user i/o pi n provides an optional bus-hold feature. the bus-hold circuitry can hold the signal on an i/o pin at its last-driven state. since the bus-hold feature holds the last-driven state of the pin until the next inpu t signal is present, an external pull-up or pull- down resistor is not necessary to hold a signal level when the bus is tri- stated. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. 1 if the bus-hold feature is enable d, the device cannot use the programmable pull-up option. di sable the bus-hold feature when the i/o pin is configured for differential signals. bus hold circuitry is not available on the dedicated clock pins. the bus-hold circuitry is only active after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to pull the signal level to the last-driven state. refer to the dc characteristics & timing specifications chapter in volume 1 of the cyclone ii devi ce handbook for the specific sustaining current for each v ccio voltage level driven through the resistor and overdrive current used to identify the next driven input level.
2?52 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features programmable pull-up resistor each cyclone ii device i/o pin provid es an optional programmable pull- up resistor during user mode. if you enable this feature for an i/o pin, the pull-up resistor (typically 25 k ) holds the output to the v ccio level of the output pin?s bank. 1 if the programmable pull-up is enabled, the device cannot use the bus-hold feature. the prog rammable pull-up resistors are not supported on the dedicated configuration, jtag, and dedicated clock pins.
altera corporation 2?53 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture advanced i/o standard support table 2?18 shows the i/o standards supported by cyclone ii devices and which i/o pins support them. table 2?18. cyclone ii supported i/o standar ds & constraints (part 1 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins 3.3-v lvttl and lvcmos single ended 3.3 v/ 2.5 v 3.3 v vvv v v 2.5-v lvttl and lvcmos single ended 3.3 v/ 2.5 v 2.5 v vvv v v 1.8-v lvttl and lvcmos single ended 1.8 v/ 1.5 v 1.8 v vvv v v 1.5-v lvcmos single ended 1.8 v/ 1.5 v 1.5 v vvv v v sstl-2 class i voltage referenced 2.5 v 2.5 v vvv v v sstl-2 class ii voltage referenced 2.5 v 2.5 v vvv v v sstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v sstl-18 class ii voltage referenced 1.8 v 1.8 v vv (1) (1) (1) hstl-18 class i voltage referenced 1.8 v 1.8 v vvv v v hstl-18 class ii voltage referenced 1.8 v 1.8 v vv (1) (1) (1) hstl-15 class i voltage referenced 1.5 v 1.5 v vvv v v hstl-15 class ii voltage referenced 1.5 v 1.5 v vv (1) (1) (1) pci and pci-x (2) single ended 3.3 v 3.3 v vv v differential sstl-2 class i or class ii pseudo differential (3) (4) 2.5 v v 2.5 v (4) v (5) v (5) differential sstl-18 class i or class ii pseudo differential (3) (4) 1.8 v v (6) 1.8 v (4) v (5) v (5)
2?54 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features f for more information on cyclone ii supported i/o standards, see the selectable i/o standards in cyclone ii devices chapter in volume 1 of the cyclone ii devi ce handbook . high-speed differe ntial interfaces cyclone ii devices can transmit and receive data through lvds signals at a data rate of up to 640 mbps and 805 mbps, respectively. for the lvds transmitter and receiver, the cyclone i i device?s input and output pins support serialization and deserial ization through internal logic. differential hstl-15 class i or class ii pseudo differential (3) (4) 1.5 v v (6) 1.5 v (4) v (5) v (5) differential hstl-18 class i or class ii pseudo differential (3) (4) 1.8 v v (6) 1.8 v (4) v (5) v (5) lvds differential 2.5 v 2.5 v vvv v v rsds and mini-lvds (7) differential (4) 2.5 v vvv lvpecl ( 8 ) differential 3.3 v/ 2.5 v/ 1.8 v/ 1.5 v (4) vv notes to table 2?18 : (1) these pins support sstl-18 class ii an d 1.8- and 1.5-v hstl class ii inputs. (2) pci-x does not meet the iv curve requirement at the linear region. pci-clamp diode is not available on top and bottom i/o pins. (3) pseudo-differential hstl and sstl outputs use two si ngle-ended outputs with the second output programmed as inverted. pseudo-differential hstl and sstl inputs treat differential in puts as two single-ended hstl and sstl inputs and only decode one of them. (4) this i/o standard is not supported on these i/o pins. (5) this i/o standard is only suppo rted on the dedicated clock pins. (6) pll_out does not support differential sstl-18 class ii and differential 1.8 and 1.5-v hstl class ii. (7) mini-lvds and rsds are only supported on output pins. (8) lvpecl is only supported on clock inputs. table 2?18. cyclone ii supported i/o standar ds & constraints (part 2 of 2) i/o standard type v ccio level top & bottom i/o pins side i/o pins input output clk, dqs user i/o pins clk, dqs pll_out user i/o pins
altera corporation 2?55 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture the reduced swing differential signaling (rsds) and mini-lvds standards are derivatives of the lvds standard. the rsds and mini- lvds i/o standards are similar in el ectrical characteristics to lvds, but have a smaller voltage swing and therefore provide increased power benefits and reduced electromagneti c interference (emi). cyclone ii devices support the rsds and mini-lvds i/o standards at data rates up to 311 mbps at the transmitter. a subset of pins in each i/o bank (on both rows and columns) support the high-speed i/o interface. the dual-purpose lvds pins require an external-resistor network at the transm itter channels in addition to 100- termination resistors on receiver ch annels. these pins do not contain dedicated serialization or deserialization circuitry. therefore, internal logic performs serialization and deserialization functions. cyclone ii pin tables list the pins that support the high-speed i/o interface. the number of lvds channels supported in each device family member is listed in table 2?19 . table 2?19. cyclone ii device lvds channels (part 1 of 2) device pin count number of lvds channels (1) ep2c5 144 31 (35) 208 56 (60) 256 61 (65) ep2c8 144 29 (33) 208 53 (57) 256 75 (79) ep2c20 240 45 (53) 256 52 (60) 484 128 (136) ep2c35 484 131 (139) 672 201 (209) ep2c50 484 119 (127) 672 189 (197)
2?56 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features you can use i/o pins and internal lo gic to implement a high-speed i/o receiver and transmitter in cyclone ii devices. cyclone ii devices do not contain dedicated seriali zation or deserialization circuitry. therefore, shift registers, internal plls, and ioes are used to perform serial-to- parallel conversions on incoming data and parallel-to-serial conversion on outgoing data. the maximum internal clock frequency for a receiver and for a transmitter is 402.5 mhz. the maximum input data rate of 805 mbps and the maximum output data rate of 64 0 mbps is only achieved when ddio registers are used. the lvds standard does not require an input reference voltage, but it does require a 100- termination resistor between the two signals at the input buffer. an external resistor network is required on the transmitter side. f for more information on cyclone ii di fferential i/o interfaces, see the high-speed differential int erfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . series on-chip termination on-chip termination helps to prevent reflections and maintain signal integrity. this also minimizes the need for external resistors in high pin count ball grid array (bga) packag es. cyclone ii devices provide i/o driver on-chip impedance matching and on-chip series termination for single-ended outputs and bidirectional pins. ep2c70 672 160 (168) 896 257 (265) note to table 2?19 : (1) the first number represents the number of bidirectional i/o pins which can be used as inputs or outputs. the number in parenthesis includes dedicated clock input pin pairs which can only be used as inputs. table 2?19. cyclone ii device lvds channels (part 2 of 2) device pin count number of lvds channels (1)
altera corporation 2?57 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture cyclone ii devices support driver im pedance matching to the impedance of the transmission line, typically 25 or 50 . when used with the output drivers, on-chip termination sets th e output driver impedance to 25 or 50 . cyclone ii devices also support i/o driver series termination (r s = 50 ) for sstl-2 and sstl-18. table 2?20 lists the i/o standards that support impedance matching and series termination. 1 the recommended frequency rang e of operation is pending silicon charac terization. on-chip series termination can be supported on any i/o bank. v ccio and v ref must be compatible for all i/o pins in order to enable on-chip series termination in a given i/o bank. i/o standards that support different r s values can reside in the same i/o bank as long as their v ccio and v ref are not conflicting. 1 when using on-chip series termination, programmable drive strength is not available. impedance matching is implemented us ing the capabilities of the output driver and is subject to a certain degr ee of variation, depending on the process, voltage and temperature. the actual tolerance is pending silicon characterization. table 2?20. i/o standards supporting series termination note (1) i/o standards target r s ( )v ccio (v) 3.3-v lvttl and lvcmos 25 (2) 3.3 2.5-v lvttl and lvcmos 50 (2) 2.5 1.8-v lvttl and lvcmos 50 (2) 1.8 sstl-2 class i 50 (2) 2.5 sstl-18 class i 50 (2) 1.8 notes to ta b l e 2 ? 2 0 : (1) supported conditions are v ccio =v ccio 50 mv. (2) these r s values are nominal values. actual impedance varies across process, voltage, and temperature conditions.
2?58 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features i/o banks the i/o pins on cyclone ii devices are grouped together into i/o banks and each bank has a separate power bus. ep2c5 and ep2c8 devices have four i/o banks (see figure 2?28 ), while ep2c20, ep 2c35, ep2c50, and ep2c70 devices have eight i/o banks (see figure 2?29 ). each device i/o pin is associated with one i/o bank . to accommodate voltage-referenced i/o standards, each cyclone ii i/o ba nk has a vref bus. each bank in ep2c5, ep2c8, ep2c20, ep2c35, and ep2c50 devices supports two vref pins and each bank of ep2c70 support s three vref pins. when using the vref pins, each vref pin must be properly connected to the appropriate voltage level. in the event these pins are not used as vref pins, they may be used as regular i/o pins. the top and bottom i/o banks (ban ks 2 and 4 in ep2c5 and ep2c8 devices and banks 3, 4, 7, and 8 in ep2c20, ep2c35, ep2c50, and ep2c70 devices) support all i/o standards listed in table 2?18 , except the pci/pci-x i/o standards. the left an d right side i/o banks (banks 1 and 3 in ep2c5 and ep2c8 devices and banks 1, 2, 5, and 6 in ep2c20, ep2c35, ep2c50, and ep2c70 devices) suppo rt i/o standards listed in table 2?18 , except sstl-18 class ii, hstl-18 cl ass ii, and hstl-15 class ii i/o standards. see table 2?18 for a complete list of supported i/o standards. the top and bottom i/o banks (ban ks 2 and 4 in ep2c5 and ep2c8 devices and banks 3, 4, 7, and 8 in ep2c20, ep2c35, ep2c50, and ep2c70 devices) support ddr2 memory up to 167 mhz/333 mbps and qdr memory up to 167 mhz/668 mbps. the left and right side i/o banks (1 and 3 of ep2c5 and ep2c8 devices and 1, 2, 5, and 6 of ep2c20, ep2c35, ep2c50, and ep2c70 devices) on ly support sdr and ddr sdram interfaces. all the i/o banks of the cyclone ii devices support sdr memory up to 167 mhz/167 mbps and ddr memory up to 167 mhz/333 mbps.
altera corporation 2?59 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture figure 2?28. ep2c5 & ep2c8 i/o banks notes (1) , (2) notes to figure 2?28 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. refer to the pi n list and the quartus ii software for exact pin locations. (3) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (5) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 1 all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (3) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (4) differential sstl-18 (4) differential hstl-18 (5) differential hstl-15 (5) i/o bank 3 also supports the 3.3-v pci & pci- x i/o standards i/o bank 1 also supports the 3.3-v pci & pci-x i/o standards individual power bus i/o bank 2 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o bank 4 also supports the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards
2?60 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features figure 2?29. ep2c20, ep2c35, ep 2c50 & ep2c70 i/o banks notes (1) , (2) notes to figure 2?29 : (1) this is a top view of the silicon die. (2) this is a graphic representation only. refer to the pi n list and the quartus ii software for exact pin locations. (3) the lvpecl i/o standard is only su pported on clock input pins. this i/o standard is not supported on output pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock inpu t pins and pll output clock pins. (5) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. each i/o bank has its own vccio pins. a single de vice can support 1.5-v, 1.8-v, 2.5-v, and 3.3-v interfac es; each individual bank can support a different standard with different i/o voltages. each bank also has dual- purpose vref pins to support any one of the voltage-referenced i/o bank 2 regular i/o block bank 8 regular i/o block bank 7 i/o bank 3 i/o bank 4 i/o bank 1 i/o bank 5 i/o bank 6 individual power bus all i/o banks support 3.3-v lvttl/lvcmos 2.5-v lvttl/lvcmos 1.8-v lvttl/lvcmos 1.5-v lvcmos lvds rsds mini-lvds lvpecl (3) sstl-2 class i and ii sstl-18 class i hstl-18 class i hstl-15 class i differential sstl-2 (4) differential sstl-18 (4) differential hstl-18 (5) differential hstl-15 (5) i/o banks 3 & 4 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 7 & 8 also support the sstl-18 class ii, hstl-18 class ii, & hstl-15 class ii i/o standards i/o banks 5 & 6 also support the 3.3-v pci & pci-x i/o standard s i/o banks 1 & 2 also support the 3.3-v pci & pci-x i/o standards
altera corporation 2?61 november 2005 cyclone ii device handbook, volume 1 cyclone ii architecture standards (e.g., sstl-2) independently. if an i/o bank does not use voltage-referenced standards, the vref pins are available as user i/o pins. each i/o bank can support multiple standards with the same v ccio for input and output pins. for example, when v ccio is 3.3-v, a bank can support lvttl, lvcmos, and 3.3-v pci for inputs and outputs. voltage- referenced standards can be supported in an i/o bank using any number of single-ended or differential standa rds as long as they use the same v ref and a compatible v ccio value. multivolt i/o interface the cyclone ii architecture supports th e multivolt i/o interface feature, which allows cyclone ii devices in all packages to interface with systems of different supply voltages. cyclone ii devices have one set of v cc pins ( vccint ) that power the internal device logic array and input buffers that use the lvpecl, lvds, hstl, or sstl i/o standards. cyclone ii devices also have four or eight sets of vcc pins ( vccio ) that power the i/o output drivers and input buffers th at use the lvttl, lvcmos, or pci i/o standards. the cyclone ii vccint pins must always be co nnected to a 1.2-v power supply. if the v ccint level is 1.2 v, then input pi ns are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-v, 1.8-v, 2.5-v, or 3.3-v power supply, depending on the output requirements. the output levels are co mpatible with systems of the same voltage as the power supply (i.e., when vccio pins are connected to a 1.5-v power supply, the output levels are compatible with 1.5-v systems). when vccio pins are connected to a 3.3-v power supply, the output high is 3.3-v and is compatible with 3.3-v systems. table 2?21 summarizes cyclone ii multivolt i/o support. table 2?21. cyclone ii multivolt i/o support (part 1 of 2) note (1) v ccio (v) input signal output signal 1.5 v 1.8 v 2.5 v 3.3 v 1.5 v 1.8 v 2.5 v 3.3 v 1.5 vv v (2) v (2) v 1.8 v (4) v v (2) v (2) v (3) v 2.5 vv v (5) v (5) v
2?62 altera corporation cyclone ii device handbook, volume 1 november 2005 i/o structure & features 3.3 v (4) v v (6) v (6) v (6) v notes to table 2?21 : (1) the pci clamping diode must be disabled to drive an input with voltages higher than v ccio . (2) when v ccio = 1.5-v or 1.8-v and a 2.5-v or 3.3-v input signal feeds an input pin, higher pin leakage current is expected. (3) when v ccio = 1.8-v, a cyclone ii device can drive a 1.5-v device with 1.8-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin or when v ccio = 1.8-v and a 1.5-v input signal feeds an input pin, the v ccio supply current will be slightly larger than expected. the reason for this increase is that the input signal level does not drive to the v ccio rail, which causes the input buff er to not completely shut off. (5) when v ccio = 2.5-v, a cyclone ii device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (6) when v ccio = 3.3-v, a cyclone ii device can drive a 1.5-v, 1.8-v, or 2.5-v device with 3.3-v tolerant inputs. table 2?21. cyclone ii multivolt i/o support (part 2 of 2) note (1) v ccio (v) input signal output signal 1.5 v 1.8 v 2.5 v 3.3 v 1.5 v 1.8 v 2.5 v 3.3 v
altera corporation 3?1 july 2005 preliminary 3. configuration & testing ieee std. 1149.1 (jtag) boundary scan support all cyclone ? ii devices provide jtag bst ci rcuitry that complies with the ieee std. 1149.1. jtag bounda ry-scan testing can be performed either before or after, but not during configuration. cyclone ii devices can also use the jtag port for configuration with the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). cyclone ii devices support ioe i/o standard reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this capability for jtag testing before configuration when some of the cyclone ii pins drive or receive from other devices on the board using voltage-referenced standards. since the cyclone ii device might not be configured before jtag testing, the i/o pins may not be configured for appropriate electrical standards for chip-to-chip communication. pr ogramming the i/o standards via jtag allows you to fully test i /o connections to other devices. f for information on i/o reconfiguration, see morphio: an i/o reconfiguration solution for altera devices white paper . a device operating in jtag mode uses four required pins: tdi , tdo , tms , and tck . the tck pin has an internal weak pull-down resister, while the tdi and tms pins have weak internal pull-up resistors. the tdo output pin and all jtag input pin voltage is determined by the v ccio of the bank where it resides. the bank v ccio selects whether the jtag inputs are 1.5-, 1.8-, 2.5-, or 3.3-v compatible. cii51003-2.0
3?2 altera corporation cyclone ii device handbook, volume 1 july 2005 ieee std. 1149.1 (jtag) boundary scan support cyclone ii devices also use the jtag port to monitor the logic operation of the device wi th the signaltap ? ii embedded logic analyzer. cyclone ii devices support the jtag instructions shown in table 3?1 . table 3?1. cyclone ii jtag in structions (part 1 of 2) jtag instruction instruction code description sample/preload 00 0000 0101 allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 1111 allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defi ned by the data in the boundary-scan register. icr instructions used when configuring a cyclone ii device via the jtag port with a usb blaster ? , byteblaster ? ii, masterblaster ? or byteblastermv ? download cable, or when using a jam file or jbc file via an embedded processor. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected.
altera corporation 3?3 july 2005 cyclone ii device handbook, volume 1 configuration & testing the quartus ii software has an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checksum is automatically loaded to the usercode register. in the settings dialog box in the assignments menu, click device & pin options , then general, and then turn on the auto usercode option . config_io 00 0000 1101 allows configuration of i/o st andards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction holds nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operat ion with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest. table 3?1. cyclone ii jtag in structions (part 2 of 2) jtag instruction instruction code description
3?4 altera corporation cyclone ii device handbook, volume 1 july 2005 signaltap ii embedded logic analyzer the cyclone ii device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for cyclone ii devices. for more information on the cyclone i i jtag specifications, refer to the dc characteristics & timing specifications chapter in the cyclone ii device handbook, volume 1 . signaltap ii embedded logic analyzer cyclone ii devices support the signaltap ii embedded logic analyzer, which monitors design operation over a period of time through the ieee std. 1149.1 (jtag) circuitry. you ca n analyze internal logic at speed without bringing intern al signals to the i/o pi ns. this feature is particularly important for advanced packages, such as fineline bga ? packages, because it can be difficul t to add a connection to a pin during the debugging process after a board is designed and manufactured. table 3?2. cyclone ii boundary-scan register length device boundary-scan register length ep2c5 498 ep2c8 597 ep2c20 969 ep2c35 1,449 ep2c50 1,374 ep2c70 1,890 table 3?3. 32-bit cyclone ii device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) man ufacturer identity (11 bits) lsb (1 bit) (2) ep2c5 0000 0010 0000 1011 0001 000 0110 1110 1 ep2c8 0000 0010 0000 1011 0010 000 0110 1110 1 ep2c20 0000 0010 0000 1011 0011 000 0110 1110 1 ep2c35 0000 0010 0000 1011 0100 000 0110 1110 1 ep2c50 0000 0010 0000 1011 0101 000 0110 1110 1 ep2c70 0000 0010 0000 1011 0110 000 0110 1110 1 notes to ta b l e 3 ? 3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1.
altera corporation 3?5 july 2005 cyclone ii device handbook, volume 1 configuration & testing f for more information on the signaltap ii, see the signal tap chapter of the quartus ii handbook, volume 3 . configuration the logic, circuitry, and interconnects in the cyclone ii architecture are configured with cmos sram elem ents. altera fp ga devices are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. cyclone ii devices are configured at sy stem power-up with data stored in an altera configuration device or provided by a system controller. the cyclone ii device?s optimized interf ace allows the device to act as controller in an active serial conf iguration scheme with epcs serial configuration devices. the serial configuration device can be programmed via srunner, the bytebl aster ii or usb blaster download cable, the altera programming unit (apu), or third-party programmers. in addition to epcs serial configuration devices, altera offers in-system programmability (isp)-capable configur ation devices that can configure cyclone ii devices via a serial data st ream using the passive serial (ps) configuration mode. the ps interfac e also enables microprocessors to treat cyclone ii devices as memory and configure them by writing to a virtual memory location, simplifying reconfiguration. after a cyclone ii device has been configured, it can be reconfigured in-circuit by resetting the device and loading new configurat ion data. real-time changes can be made during system operation, enabling innovative reconfigurable applications. operating modes the cyclone ii architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sram data into the device is called configuration. during initialization, which occurs immediately after configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow cyclone ii devices to be reconfigured in-circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with the nconfig pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-fiel d upgrades by distributing new configuration files within the system or remotely.
3?6 altera corporation cyclone ii device handbook, volume 1 july 2005 configuration schemes a built-in weak pull-up resistor pulls all user i/o pins to v ccio before and during device configuration. the configuration pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the voltage level of the configuration output pins is determined by the v ccio of the bank where the pins reside. the bank v ccio selects whether the configuration in puts are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. configuration schemes you can load the configuration data for a cyclone ii device with one of three configuration schemes (see table 3?4 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a cyclone ii device. a low-cost configuration device can automatically configure a cyclone ii device at system power-up. multiple cyclone ii devices can be configured in any of the three configuration schemes by connect ing the configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. f for more information on configuration, see the configuring cyclone ii devices chapter of the cyclone ii handbook, volume 2 . cyclone ii automated single event upset detection cyclone ii devices offer on-chip circ uitry for automated checking of single event upset (seu) detection. some applications that require the device to operate error free at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy code (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to en sure data reliability and is one of the best options for mitigating seu. table 3?4. data sources for configuration configuration scheme data source active serial (as) low-cost serial configuration device passive serial (ps) enhanced or epc2 c onfiguration device, masterblaster, byteblastermv, byteblaster ii or usb blaster download cable, or serial data source jtag masterblaster, byteblastermv, bytebl aster ii or usb blaster download cable or a microprocessor with a jam or jbc file
altera corporation 3?7 july 2005 cyclone ii device handbook, volume 1 configuration & testing you can implement the error detection crc feature with existing circuitry in cyclone ii devices, eliminating the need for external logic. for cyclone ii devices, the crc is computed by the device during configuration and checked against an automatically computed crc during normal operation. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry in the cyclone i i devices performs error detection automatically. this error detection circuitry in cyclone ii devices constantly checks for errors in the configuration sram cells while the device is in user mode. you can monitor one external pin for the error and use it to trigger a re-configuration cy cle. you can select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc checker between 400 khz to 80 mhz. this controls the rate that the crc circuitr y verifies the internal configuration sram bits in the fpga device. f for more information on crc, refer to the error detection using crc in altera fpgas application note.
3?8 altera corporation cyclone ii device handbook, volume 1 july 2005 cyclone ii automated single event upset detection
altera corporation 4?1 july 2005 preliminary 4. hot socketing & power-on reset introduction cyclone? ii devices offer hot socketin g (also known as hot plug-in, hot insertion, or hot swap) and power se quencing support without the use of any external devices. you can insert or remove a cyclone ii board in a system during system operation wi thout causing undesirable effects to the board or to the running system bus. the hot-socketing feature lessens the board design difficulty when using cyclone ii devices on printed circuit boards (pcbs) that also contain a mixture of 3.3-, 2.5-, 1.8-, and 1. 5-v devices. with the cyclone ii hot-socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. the cyclone ii hot-socketing feature provides: board or device insertion and removal without external components or board manipulation support for any power-up sequence non-intrusive i/o buffers to system buses during hot insertion this chapter also discusses the po wer-on reset (por) circuitry in cyclone ii devices. the por circuitry keeps the devices in the reset state until the v cc is within operating range. cyclone ii hot-socketing specifications cyclone ii devices offer hot-socketing capability with all three features listed above without any external components or special design requirements. the hot-socketing featur e in cyclone ii devices offers the following: the device can be driven before power-up without any damage to the device itself. i/o pins remain tri-stated during power-up. the device does not drive out before or during power- up, thereby affecting other buses in operation. there are no internal current paths from i/o pins to v ccio or v ccint power supplies. signals driven in on i/o pins do not power the v ccio or v ccint power buses. cii51004-2.0
4?2 altera corporation cyclone ii device handbook, volume 1 july 2005 cyclone ii hot-socketing specifications devices can be driv en before power-up you can drive signals into the i/o pins, dedicated input pins, and dedicated clock pins of cyclone ii devi ces before or during power-up or power-down without damaging the device. cyclone ii devices support any power-up or power-down sequence (v ccio and v ccint ) to simplify system level design. i/o pins remain tri-stated during power-up a device that does not support ho t socketing may interrupt system operation or cause contention by driv ing out before or during power-up. in a hot-socketing situation, the cyclone ii device?s output buffers are turned off during system power- up or power-down. the cyclone ii device also does not drive out until the device is configured and has attained proper operating conditions. signal pins do not have internal current paths to v ccio or v ccint power supplies devices that do not support hot socketing can short power supplies together when powered-up through the device signal pins. this irregular power-up can damage both the driving and driven devices and can disrupt card power-up. cyclone ii devices do not have a curr ent path from i/o pins, dedicated input pins, or dedicated clock pins to the v ccio or v ccint pins before or during power-up. a cyclone ii device may be inserted into (or removed from) a powered-up system board with out damaging or interfering with system-board operation. when hot socketing, cyclone ii devices may have a minimal effect on the signal integrity of the backplane. 1 you can power up or power down the v ccio and v ccint pins in any sequence. the power supply ramp rates can range from 100 s to 100 ms. both v cc supplies must power down within 100 ms of each other to prevent i/o pins from driving out. during hot socketing, the i/o pin capacitance is less than 15 pf and the clock pin capacitance is less than 20 pf. cyclone ii devices meet the following hot-socketing specification. the hot-socketing dc specification is: | i iopin | < 300 a the hot-socketing ac specification is: | i iopin | < 8 ma or | i iopin | > 8 ma for 10 ns or less
altera corporation 4?3 july 2005 cyclone ii device handbook, volume 1 hot socketing & power-on reset i iopin is the current at any user i/o pin on the device. the ac specification has two requirements. th e peak current during power-up or power-down is < 8 ma. the peak curr ent can exceed 8 ma for 10 ns or less. a possible concern for semiconducto r devices in general regarding hot socketing is the potential for latch-up . latch-up can occur when electrical subsystems are hot socketed into an ac tive system. during hot socketing, the signal pins may be connected and driven by the active system before the power supply can provide current to the device?s v cc and ground planes. this condition can lead to latch-up and cause a low-impedance path from v cc to ground within the device. as a result, the device extends a large amount of current, possibly causing electrical damage. altera has ensured by design of the i/o buffers and hot-socketing circuitry, that cyclone ii devices are immune to latch-up during hot socketing. hot-socketing feature implementation in cyclone ii devices the hot-socketing feature turns off th e output buffer during power up (either v ccint or v ccio supplies) or power down. the hot-socket circuit generates an internal hotsckt signal when either v ccint or v ccio is below the threshold voltag e. designs cannot use the hotsckt signal for other purposes. the hotsckt signal cuts off the output buffer to ensure that no dc current (except for we ak pull-up leakag e current) leaks through the pin. when v cc ramps up slowly, v cc is still relatively low even after the internal por signal (not available to the fpga fabric used by customer designs) is released and the configuration is finished. the conf_done , nceo , and nstatus pins fail to respon d, as the output buffer cannot drive out because the ho t-socketing circuitry keeps the i/o pins tristated at this low v cc voltage. therefore, the hot-socketing circuit has been removed on these configurat ion output or bidirectional pins to ensure that they are able to operate during configuration. these pins are expected to drive out during power-up and power-down sequences. each i/o pin has the circuitry shown in figure 4?1 .
4?4 altera corporation cyclone ii device handbook, volume 1 july 2005 hot-socketing feature implementation in cyclone ii devices figure 4?1. hot-socketing circuit bloc k diagram for cyclone ii devices the por circuit monitors v ccint voltage level and keeps i/o pins tri- stated until the device is in user mode. the weak pull-up resistor (r) from the i/o pin to v ccio keeps the i/o pins from floating. the voltage tolerance control circuit permits the i/o pins to be driven by 3.3 v before v ccio and/or v ccint are powered, and it prevents the i/o pins from driving out when the device is not in user mode. the hot socket circuit prevents i/o pins from internally powering v ccio and v ccint when driven by external signals before the device is powered. f for more information, see the dc characteristics & timing specifications chapter in volume 1 of the cyclone ii device handbook for the value of the internal weak pull-up resistors. figure 4?2 shows a transistor level cross section of the cyclone ii device i/o buffers. this design ensures th at the output buffers do not drive when v ccio is powered before v ccint or if the i/o pad voltage is higher than v ccio . this also applies for sudden voltage spikes during hot socketing. there is no current path from signal i/o pins to v ccint or v ccio during hot socketing. the v pa d leakage current charges the voltage tolerance control circuit capacitance. output enable output hot socket output pre-driver voltage tolerance control power-on reset monitor weak pull-up resistor pad input buffer to logic array r
altera corporation 4?5 july 2005 cyclone ii device handbook, volume 1 hot socketing & power-on reset figure 4?2. transistor level diagram of fpga device i/o buffers note to figure 4?2 : (1) this is the logic array signal or the larger of either the v ccio or v pa d signal. (2) this is the larger of either the v ccio or v pad signal. power-on reset circuitry cyclone ii devices have a por circuit to keep the whole device system in reset state until the power supply voltage levels have stabilized during power-up. the por ci rcuit monitors the v ccint and v ccio voltage levels and tri-states all the user i/o pins while v cc is ramping up until normal user levels are reached. the por circuitry also ensures that the v ccio level of the two i/o banks that contains configuration pins (i/o banks 1 and 3 for ep2c5 and ep2c8, i/o ba nks 2 and 6 for ep2c20, ep2c35, ep2c50, and ep2c70) as well as the logic array v ccint voltage reach an acceptable level before configuration is triggered. after the cyclone ii device enters user mode, the por circuit continues to monitor the v ccint voltage level so that a brown-out condition during user mode can be detected. if there is a v ccint voltage sag below the por trip point at ~600 to 700 mv during user mode, the por circuit resets the device. if there is a v ccio voltage sag during user mode, the por circuit does not reset the device. when power is applied to a cyclone i i device, a por event occurs if v cc reaches the recommended operating rang e within a certain period of time (specified as a maximum v cc rise time). the maximum v cc rise time for cyclone ii devices is 100 ms. the minimum por time is 100 ms for cyclone ii devices. however, you can extend initialization time by asserting the nstatus pin using an external component. logic array signal (1) (2) v ccio v pad n+ n+ n-well n+ p+ p+ p-well p-substrate
4?6 altera corporation cyclone ii device handbook, volume 1 july 2005 conclusion conclusion cyclone ii devices are hot socketable and support all power-up and power-down sequences with the one requirement that v ccio and v ccint be powered up and down within 100 ms of each other to keep the i/o pins from driving out. cyclone ii devices do not require any external devices for hot socketing and power sequencing.
altera corporation 5?1 march 2006 preliminary 5. dc characteristics & timing specifications operating conditions cyclone? ii devices are offered in commercial, industrial, and extended temperature grades. commercial devices are offered in -6 (fastest), -7, -8 speed grades. all parameter limits are representati ve of worst-case supply voltage and junction temperature conditions. unle ss otherwise noted, the parameter values in this chapter apply to all cyclone ii devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. al l parameters representing voltages are measured with respect to ground. tables 5?1 through 5?4 provide information on absolute maximum ratings. table 5?1. cyclone ii device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 1.8 v v ccio output supply voltage ?0.5 4.6 v v in dc input voltage (3) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias 125 c notes to ta b l e 5 ? 1 : (1) conditions beyond those listed in this table cause pe rmanent damage to a device. these are stress ratings only. functional operation at these levels or any other conditions beyond those specified in this chapter is not implied. additionally, device operation at the absolute maximum ra tings for extended periods of time may have adverse affects on the device reliability. (2) see the operating requirements for altera devices data sheet for more information. (3) during transitions, the inputs may over shoot to the voltage shown in table 5?4 based upon the input duty cycle. the dc case is equivalent to 100% duty cycle. during transition, the inputs may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. cii51005-2.3
5?2 altera corporation cyclone ii device handbook, volume 1 march 2006 operating conditions table 5?2 specifies the recommended operating conditions for cyclone ii devices. it shows the allowed voltage ranges for v ccint , v ccio , and the operating junction temperature (t j ). the lvttl and lvcmos inputs are powered by v ccio only. the lvpecl input buffers on dedicated clock pins are powered by v ccint . the sstl, hstl, lvds input buffers are powered by both v ccint and v ccio . table 5?2. recommended operating conditions symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (1) 1.15 1.25 v v ccio (2) supply voltage for output buffers, 3.3-v operation (1) 3.135 (3.00) 3.465 (3.60) (3) v supply voltage for output buffers, 2.5-v operation (1) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (1) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (1) 1.425 1.575 v t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c for extended temperature use ?40 125 c notes to ta b l e 5 ? 2 : (1) the maximum v cc (both v ccio and v ccint ) rise time is 100 ms, and v cc must rise monotonically. (2) the v ccio range given here spans the lowest and highest oper ating voltages of all supp orted i/o standards. the recommended v ccio range specific to each of the sing le-ended i/o standards is given in table 5?6 , and those specific to the differential standards is given in table 5?8 . (3) the minimum and maximum values of 3.0 v and 3.6 v, respectively, for v ccio only applies to the pci and pci-x i/o standards. see table 5?6 for the voltage range of other i/o standards.
altera corporation 5?3 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?3. dc characteristic s for user i/o, dual-purpose & dedicated pins symbol parameter conditions minimum typical maximum unit v in input voltage (1) , (2) ?0.5 4.0 v i i input pin leakage current v i = v cciomax to 0 v (3) ?10 10 a v out output voltage 0 v ccio v i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (3) ?10 10 a i ccint0 v ccint supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c nominal v ccint ep2c5 0.010 (4) a ep2c8 0.017 (4) a ep2c20 0.037 (4) a ep2c35 0.066 (4) a ep2c50 0.101 (4) a ep2c70 0.141 (4) a i ccio0 v ccio supply current (standby) v i = ground, no load, no toggling inputs t j = 25 c v ccio = 2.5 v ep2c5 0.7 (4) ma ep2c8 0.8 (4) ma ep2c20 0.9 (4) ma ep2c35 1.3 (4) ma ep2c50 1.3 (4) ma ep2c70 1.7 (4) ma r conf value of i/o pin pull-up resistor before and during configuration v ccio = 3.3 v 10% (5) 10 25 50 k v ccio = 2.5 v 5% (5) 15 35 60 k v ccio = 1.8 v 5% (5) 30 65 120 k v ccio = 1.5 v 5% (5) 40 85 140 k notes to ta b l e 5 ? 3 : (1) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (2) the minimum dc input is ?0.5 v. du ring transitions, the inputs may unde rshoot to ?2.0 v or overshoot to the voltages shown in table 5?4 , based on input duty cycle for input curren ts less than 100 ma. the overshoot is dependent upon duty cycle of the signal. the dc case is eq uivalent to 100% duty cycle. (3) this value is specified for normal device operation. the value may vary during powe r-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (4) maximum values depend on the actual t j and design utilization. see the excel-based powerplay early power estimator ( www.altera.com ) or the quartus ii powerplay power analyzer feature for maximum values. see the section ?power consumption? on page 5?13 for more information. (5) pin pull-up resistance values lower if an external source drives the pin higher than v ccio .
5?4 altera corporation cyclone ii device handbook, volume 1 march 2006 operating conditions table 5?4 shows the maximum v in overshoot voltage and the dependency on the duty cycl e of the input signal. see table 5?3 for more information. table 5?4. v in overshoot voltage fo r all input buffers maximum v in (v) input signal duty cycle 4.0 100% (dc) 4.1 90% 4.2 50% 4.3 30% 4.4 17% 4.5 10%
altera corporation 5?5 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications single-ended i/o standards tables 5?6 and 5?7 provide operating condition information when using single-ended i/o standards with cyclone ii devices. table 5?5 provides descriptions for the voltage and current symbols used in tables 5?6 and 5?7 . table 5?5. voltage & curr ent symbol definitions symbol definition v ccio supply voltage for single-ended inputs and for output drivers v ref reference voltage for setting the input switching threshold v il input voltage that indicates a low logic level v ih input voltage that indicates a high logic level v ol output voltage that indicates a low logic level v oh output voltage that indicates a high logic level i ol output current condition under which v ol is tested i oh output current condition under which v oh is tested v tt voltage applied to a resistor termination as specified by hstl and sstl standards table 5?6. recommended operating conditions for user i/o pins using single-ended i/o standards (part 1 of 2) note (1) i/o standard v ccio (v) v ref (v) v il (v) v ih (v) min typ max min typ max max min 3.3-v lvttl and lvcmos 3.135 3.3 3.465 0.8 1.7 2.5-v lvttl and lvcmos 2.375 2.5 2.625 0.7 1.7 1.8-v lvttl and lvcmos 1.710 1.8 1.890 0.35 v ccio 0.65 v ccio 1.5-v lv c m o s 1.425 1.5 1.575 0.35 v ccio 0.65 v ccio pci and pci-x 3.000 3.3 3.600 0.3 v ccio 0.5 v ccio sstl-2 class i 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.18 (dc) v ref ? 0.35 (ac) v ref + 0.18 (dc) v ref + 0.35 (ac) sstl-2 class ii 2.375 2.5 2.625 1.19 1.25 1.31 v ref ? 0.18 (dc) v ref ? 0.35 (ac) v ref + 0.18 (dc) v ref + 0.35 (ac)
5?6 altera corporation cyclone ii device handbook, volume 1 march 2006 operating conditions sstl-18 class i 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.125 (dc) v ref ? 0.25 (ac) v ref + 0.125 (dc) v ref + 0.25 (ac) sstl-18 class ii 1.7 1.8 1.9 0.833 0.9 0.969 v ref ? 0.125 (dc) v ref ? 0.25 (ac) v ref + 0.125 (dc) v ref + 0.25 (ac) 1.8-v hstl class i 1.71 1.8 1.89 0.85 0.9 0.95 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.8-v hstl class ii 1.71 1.8 1.89 0.85 0.9 0.95 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.5-v hstl class i 1.425 1.5 1.575 0.71 0.75 0.79 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) 1.5-v hstl class ii 1.425 1.5 1.575 0.71 0.75 0.79 v ref ? 0.1 (dc) v ref ? 0.2 (ac) v ref + 0.1 (dc) v ref + 0.2 (ac) note to ta b l e 5 ? 6 : (1) nominal values (nom) are for t a = 25 c, v ccint = 1.2 v, and v ccio = 1.5, 1.8, 2.5, and 3.3 v. table 5?7. dc characteristics of user i/o pi ns using single-ended standards (part 1 of 2) notes (1) , (2) i/o standard test conditions voltage thresholds i ol (ma) i oh (ma) maximum v ol (v) minimum v oh (v) 3.3-v lvttl 4 ?4 0.45 2.4 3.3-v lvcmos 0.1 ?0.1 0.2 v ccio ? 0.2 2.5-v lvttl and lvcmos 1?1 0.4 2.0 1.8-v lvttl and lvcmos 2?2 0.45 v ccio ? 0.45 1.5-v lvttl and lvcmos 2?20.25 v ccio 0.75 v ccio pci and pci-x 1.5 ?0.5 0.1 v ccio 0.9 v ccio sstl-2 class i 8.1 ?8.1 v tt ? 0.57 v tt + 0.57 sstl-2 class ii 16.4 ?16.4 v tt ? 0.76 v tt + 0.76 sstl-18 class i 6.7 ?6.7 v tt ? 0.475 v tt + 0.475 sstl-18 class ii 13.4 ?13.4 0.28 v ccio ? 0.28 table 5?6. recommended operating conditions for user i/o pins using single-ended i/o standards (part 2 of 2) note (1) i/o standard v ccio (v) v ref (v) v il (v) v ih (v) min typ max min typ max max min
altera corporation 5?7 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications differential i/o standards the rsds and mini-lvds i/o standard s are only supported on output pins. the lvds i/o standard is suppo rted on both receiver input pins and transmitter output pins. 1 for more information on how th ese differential i/o standards are implemented, see the high-speed differenti al interfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook . figure 5?1 shows the receiver input waveforms for all differential i/o standards (lvds, lvpecl, different ial 1.5-v hstl class i and ii, differential 1.8-v hstl class i and ii, differential sstl-2 class i and ii, and differential sstl-18 class i and ii). 1.8-v hstl class i 8 ?8 0.4 v ccio ? 0.4 1.8-v hstl class ii 16 ?16 0.4 v ccio ? 0.4 1.5-v hstl class i 8 ?8 0.4 v ccio ? 0.4 1.5v hstl class ii 16 ?16 0.4 v ccio ? 0.4 note to ta b l e 5 ? 7 : (1) the values in this table are ba sed on the conditions listed in tables 5?2 and 5?6 . (2) this specification is supported across all the programmable drive settings available as shown in the cyclone ii architecture chapter of the cyclone ii device handbook . table 5?7. dc characteristics of user i/o pi ns using single-ended standards (part 2 of 2) notes (1) , (2) i/o standard test conditions voltage thresholds i ol (ma) i oh (ma) maximum v ol (v) minimum v oh (v)
5?8 altera corporation cyclone ii device handbook, volume 1 march 2006 operating conditions figure 5?1. receiver input waveform s for differential i/o standards notes to figure 5?1 : (1) v id is the differential input voltage. v id = |p ? n|. (2) v icm is the input common mode voltage. v icm = (p + n)/2. (3) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v ih negative channel (n) = v il ground v id (1) v id (1) v id (1) v icm (2) 0 v p ? n (3)
altera corporation 5?9 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?8 shows the recommended operating conditions for user i/o pins with differential i/o standards. figure 5?2 shows the transmitter output waveforms for all supported differential output standards (lvds, mini-lvds, rsds, differential 1.5-v hstl class i and ii , differential 1.8-v hstl cl ass i and ii, differential sstl-2 class i and ii , and differential ss tl-18 class i and ii). table 5?8. recommended operating conditions for user i/o pins using differ ential signal i/o standards i/o standard v ccio (v) v id (v) (1) v icm (v) v il (v) v ih (v) min typ max min typ max min typ max min max min max lvds 2.375 2.5 2.625 0.1 0.65 0.1 2.0 mini-lvds (2) 2.375 2.5 2.625 rsds (2) 2.375 2.5 2.625 lvpecl (3) 3.135 3.3 3.465 0.1 0.6 0.95 0 2.2 2.1 2.88 differential 1.5-v hstl class i and ii (4) 1.425 1.5 1.575 0.2 v ccio + 0.6 0.68 0.9 v ref ? 0.20 v ref + 0.20 differential 1.8-v hstl class i and ii (4) 1.71 1.8 1.89 v ref ? 0.20 v ref + 0.20 differential sstl-2 class i and ii (5) 2.375 2.5 2.625 0.36 v ccio + 0.6 0.5 v ccio ? 0.2 0.5 v ccio 0.5 v ccio + 0.2 v ref ? 0.35 v ref + 0.35 differential sstl-18 class i and ii (5) 1.7 1.8 1.9 0.25 v ccio + 0.6 0.5 v ccio ? 0.2 0.5 v ccio 0.5 v ccio + 0.2 v ref ? 0.25 v ref + 0.25 notes to ta b l e 5 ? 8 : (1) refer to the high-speed differential interfaces in cyclone ii devices chapter in volume 1 of the cyclone ii device handbook for measurement conditions on v id . (2) the rsds and mini-lvds i/o standard s are only supported on output pins. (3) the lvpecl i/o standard is only supported on clock in put pins. this i/o standard is not supported on output pins. (4) the differential 1.8-v and 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. (5) the differential sstl-18 and sstl-2 i/o standards are only supported on clock input pins and pll output clock pins.
5?10 altera corporation cyclone ii device handbook, volume 1 march 2006 operating conditions figure 5?2. transmitter output wavefo rms for differential i/o standards notes to figures 5?1 & 5?2 : (1) v od is the output differential voltage. v od = |p ? n|. (2) v ocm is the output common mode voltage. v ocm = (p + n)/2. (3) the p ? n waveform is a function of the positive channel (p) and the negative channel (n). table 5?9 shows the dc characteristics for user i/o pins with differential i/o standards. single-ended waveform differential waveform (mathematical function of positive & negative channel) positive channel (p) = v oh negative channel (n) = v ol ground v od (1) v od (1) v od (1) 0 v v ocm (2) p ? n (3) table 5?9. dc characteristics fo r user i/o pins using differ ential i/o standards (part 1 of 2) note (1) i/o standard v od (mv) v od (mv) v ocm (v) v oh (v) v ol (v) min typ max min max min typ max min max min max lvds 250 600 50 1.125 1.25 1.375 mini-lvds (2) 300 600 50 1.125 1.25 1.375 rsds (2) 100 600 1.125 1.25 1.375 differential 1.5-v hstl class i and ii (3) v ccio ? 0.4 0.4 differential 1.8-v hstl class i and ii (3) v ccio ? 0.4 0.4 differential sstl-2 class i (4) v tt + 0.57 v tt ? 0.57
altera corporation 5?11 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications dc characteristics for different pin types table 5?10 shows which types of pins that support bus hold circuitry. differential sstl-2 class ii (4) v tt + 0.76 v tt ? 0.76 differential sstl-18 class i (4) 0.5 v ccio ? 0.125 0.5 v ccio 0.5 v ccio + 0.125 v tt + 0.475 v tt ? 0.475 differential sstl-18 class ii (4) 0.5 v ccio ? 0.125 0.5 v ccio 0.5 v ccio + 0.125 v ccio ? 0.28 0.28 notes to ta b l e 5 ? 9 : (1) the lvpecl i/o standard is only supported on clock in put pins. this i/o standard is not supported on output pins. (2) the rsds and mini-lvds i/o standard s are only supported on output pins. (3) the differential 1.8-v hstl and differential 1.5-v hstl i/o standards are only supported on clock input pins and pll output clock pins. (4) the differential sstl-18 and sstl-2 i/o standards are only supported on clock input pins and pll output clock pins. table 5?9. dc characteristics fo r user i/o pins using differ ential i/o standards (part 2 of 2) note (1) i/o standard v od (mv) v od (mv) v ocm (v) v oh (v) v ol (v) min typ max min max min typ max min max min max table 5?10. bus hold support pin type bus hold i/o pins using single-ended i/o standards yes i/o pins using differential i/o standards no dedicated clock pins no jtag no configuration pins no
5?12 altera corporation cyclone ii device handbook, volume 1 march 2006 dc characteristics for different pin types table 5?11 specifies the bus hold para meters for general i/o pins. on-chip termination specifications table 5?12 defines the specifications for internal termination resistance tolerance when using series or differential on-chip termination. table 5?11. bus hold parameters note (1) parameter conditions v ccio level unit 1.8 v 2.5 v 3.3 v min max min max min max bus-hold low, sustaining current v in > v il (maximum) 30 50 70 a bus-hold high, sustaining current v in < v il (minimum) ?30 ?50 ?70 a bus-hold low, overdrive current 0 v < v in < v ccio 200 300 500 a bus-hold high, overdrive current 0 v < v in < v ccio ?200 ?300 ?500 a bus-hold trip point (2) 0.68 1.07 0.7 1.7 0.8 2.0 v notes to ta b l e 5 ? 11 : (1) there is no specification for bus-hold at v ccio = 1.5 v for the hstl i/o standard. (2) the bus-hold trip points are based on calc ulated input voltages from the jedec standard. table 5?12. series on-chip te rmination specifications symbol description conditions resistance tolerance commercial max industrial max extended temp max unit 25- r s internal series termination without calibration (25- setting ) v ccio = 3.3v 30 30 40 % 50- r s internal series termination without calibration (50- setting ) v ccio = 2.5v 30 30 40 % 50- r s internal series termination without calibration (50- setting ) v ccio = 1.8v 30 (1) 30 (1) 50 % notes for ta b l e 5 ? 1 2 : (1) for commercial and industrial ?8 devices, the tolerance is 40%.
altera corporation 5?13 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?13 shows the cyclone ii device pi n capacitance for different i/o pin types. power consumption you can calculate the power usage for your design using the powerplay early power estimator and the powerplay power analyzer feature in the quartus ? ii software. the interactive powerplay early power estimator is typically used during the early stages of fpga design , prior to finalizing the project, in order to get a magnitude estimate of the device power. the quartus ii software powerplay power analyzer fe ature is typically used during the later stages of fpga design. the po werplay power analyzer also allows you to apply test vectors against yo ur design for more accurate power consumption modeling. in both cases, only use these calculat ions as an estimation of power, not as a specification. for more informat ion on powerplay tools, refer to the powerplay early power estimator user guide and the powerplay early power estimator and powerplay power analyzer chapters in volume 3 of the quartus ii handbook. 1 you can obtain the excel-ba sed powerplay early power estimator at www.altera.com . see table 5?3 on page 5?3 for typical i cc standby specifications. the power-up current required by cy clone ii devices does not exceed the maximum static current. the rate at which the current increases is a function of the system power suppl y. the exact amount of current table 5?13. device capacitance note (1) symbol parameter typical unit c io input capacitance for user i/o pin 6 pf c lvds input capacitance for dual-purpose lvds/user i/o pin 6 pf c vref input capacitance for dual-purpose vref and user i/o pin. 21 pf c clk input capacitance for clock pin. 5 pf notes to ta b l e 5 ? 1 3 : (1) capacitance is sample-tested only. ca pacitance is measured using time-domain reflectometry (tdr). measurement accuracy is within 0.5 pf.
5?14 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications consumed varies according to the process, temperature, and power ramp rate. the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. you should select power supplies and regulators that can supply the amount of current required when designing with cyclone ii devices. altera recommends using the cy clone ii powerpla y early power estimator to estima te the user-mode i ccint consumption and then select power supplies or regulators based on the values obtained. timing specifications the directdrive? technology and multitrack? interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across al l cyclone ii device densities and speed grades. this section describes and specifies the performance, internal, external, high-speed i/o, jtag, and pll timing specifications. this section shows the timing models for cyclone ii devices. commercial devices meet this timing over the commercial temperature range. industrial devices meet this timing ov er the industrial temperature range. all specifications are representative of worst-case supply voltage and junction temperature conditions. 1 the timing numbers listed in th e tables of this section are extracted from the quartus ? ii software version 5.0 sp1. preliminary & final ti ming specifications timing models can have either prelim inary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 5?14 shows the status of the cyclone ii device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
altera corporation 5?15 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual perf ormance of the device under worst- case voltage and junction temperature conditions. performance table 5?15 shows cyclone ii performance for some common designs. all performance values were obtained by compiling lpm or megacore functions using the quartus ii software. table 5?14. cyclone ii device timing model status device preliminary final ep2c5 v ep2c8 v ep2c20 v ep2c35 v ep2c50 v ep2c70 v table 5?15. cyclone ii performance (part 1 of 3) notes (1) through (7) applications resources used performance les m4k memory blocks dsp blocks ?6 speed grade ?7 speed grade ?8 speed grade units le 16-to-1 multiplexer (3) 11 0 0 384.02 321.64 292.22 mhz 32-to-1 multiplexer (3) 24 0 0 294.2 262.32 204.24 mhz 16-bit counter 16 0 0 401.6 349.4 310.65 mhz 64-bit counter 64 0 0 155.98 138.83 126.48 mhz memory m4k block simple dual-port, single-clock ram 128x36 bit (5) , (7) 0 1 0 235.0 195.0 163.0 mhz simple dual-port, dual-clock ram 128x36 bit (6) , (7) 0 1 0 235.0 195.0 163.0 mhz true dual-port, single-clock ram 128x18 bit (5) , (7) 0 1 0 235.0 195.0 163.0 mhz true dual-port, dual-clock ram 128x18 bit (6) , (7) 0 1 0 180.0 172.0 163.0 mhz
5?16 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications single port ram 128x36 bit (7) 0 1 0 235.0 195.0 163.0 mhz rom 128x36 bit (7) 0 1 0 260.0 216.0 180.0 mhz fifo 128x36 bit (7) 24 1 0 235.0 195.0 163.0 mhz dsp block 9x9-bit multiplier (4) 0 0 1 260.01 216.73 180.57 mhz 18x18-bit multiplier (4) 0 0 2 260.01 216.73 180.57 mhz 18-bit,4tap fir filter 113 0 8 182.64 151.12 128.05 mhz larger designs 8-bit,16tap parallel fir filter 52 0 4 133.56 112.09 92.23 mhz 8-bit,1024pt,streaming, 3mults/5adders fft function 3191 22 9 139.58 118.59 99.07 mhz 8-bit,1024pt,streaming, 4mults/2adders fft function 3041 22 12 250.25 198.76 165.15 mhz 8-bit,1024pt,single output 1 parallel fft engine, burst, 3mults/5adders fft function 1056 5 3 141.54 119.16 97.98 mhz 8-bit,1024pt, single output 1 parallel fft engine, burst, 4mults/2adders fft function 1006 5 4 260.01 213.58 180.05 mhz 8-bit,1024pt,single output 2 parallel fft engines, burst, 3mults/5adders fft function 1857 10 6 141.9 119.57 96.07 mhz 8-bit,1024pt,single output 2 parallel fft engines, burst, 4mults/2adders fft function 1757 10 8 235.07 195.0 163.02 mhz 8-bit,1024pt,quad output 1 parallel fft engine, burst, 3mults/5adders fft function 2550 10 9 141.22 118.09 99.43 mhz 8-bit,1024pt,quad output 1 parallel fft engine, burst, 4mults/2adders fft function 2400 10 12 260.01 211.72 151.01 mhz 8-bit,1024pt,quad output 2 parallel fft engines, burst, 3mults/5adders fft function 4343 14 18 140.78 118.41 97.8 mhz 8-bit,1024pt,quad output 2 parallel fft engines, burst, 4mults/2adders fft function 4043 14 24 229.2 192.38 163.02 mhz table 5?15. cyclone ii performance (part 2 of 3) notes (1) through (7) applications resources used performance les m4k memory blocks dsp blocks ?6 speed grade ?7 speed grade ?8 speed grade units
altera corporation 5?17 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 8-bit,1024pt,quad output 4 parallel fft engines, burst, 3mults/5adders fft function 7496 28 36 140.98 118.11 98.16 mhz 8-bit,1024pt,quad output 4 parallel fft engines, burst, 4mults/2adders fft function 6896 28 48 235.07 195.0 163.02 mhz 8-bit,1024pt,quad output 1 parallel fft engine, buffered burst, 3mults/5adders fft function 2934 18 9 142.24 118.39 97.63 mhz 8-bit,1024pt,quad output 1 parallel fft engine, buffered burst, 4mults/2adders fft function 2784 18 12 256.47 182.01 175.46 mhz 8-bit,1024pt,quad output 2 parallel fft engines, buffered burst, 3mults/5adders fft function 4720 30 18 141.3 118.49 99.06 mhz 8-bit,1024pt,quad output 2 parallel fft engines, buffered burst, 4mults/2adders fft function 4420 30 24 235.07 195.0 163.02 mhz 8-bit,1024pt,quad output 4 parallel fft engines, buffered burst, 3mults/5adders fft function 8053 60 36 140.25 117.86 93.75 mhz 8-bit,1024pt,quad output 4 parallel fft engines, buffered burst, 4mults/2adders fft function 7453 60 48 235.07 195.0 163.02 mhz notes to table 5?15 : (1) the design performance numbers were obtained using test designs in the quartus ii software version 5.1 sp2. performance may vary depending on how the quar tus ii software places and routes your design. (2) applications that are not listed will be in cluded in a future version of the data sheet. (3) this application uses regi stered inputs and outputs. (4) this application uses registered multiplier input and output stages within the dsp block. (5) this application uses the same clock source for both a and b ports. (6) this application uses independent clock sources for a and b ports. (7) this application uses pll clock outputs that are globa lly routed to connect and drive m4k clock ports. use of non-pll clock sources or local routing to drive m4k clock ports may result in lower performance numbers than shown here. refer to the quartus ii timing report for actual performance numbers. table 5?15. cyclone ii performance (part 3 of 3) notes (1) through (7) applications resources used performance les m4k memory blocks dsp blocks ?6 speed grade ?7 speed grade ?8 speed grade units
5?18 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications internal timing see tables 5?16 through 5?19 for the internal timing parameters. table 5?16. le_ff internal timing microparameters parameter -6 speed grade -7 speed grade -8 speed grade unit minimum maximum minimum maximum minimum maximum t su 35 40 46 ps t h 266 286 306 ps t co 250 277 304 ps t clr 191 217 244 ps t pre 191 217 244 ps t clkl 1000 1111 1242 ps t clkh 1000 1111 1242 ps t lut 438 545 651 ps table 5?17. ioe internal timing microparameters parameter -6 speed grade -7 speed grade -8 speed grade unit minimum maximum minimum maximum minimum maximum t su 76 89 101 ps t h 88 97 106 ps t co 155 171 187 ps t pin2combout_r 762 784 855 ps t pin2combout_c 760 783 854 ps t combin2pin_r 2490 2689 2887 ps t combin2pin_c 2622 2831 3041 ps t clr 137 151 165 ps t pre 192 212 233 ps t clkl 1000 1111 1242 ps t clkh 1000 1111 1242 ps
altera corporation 5?19 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?18. dsp block internal timing microparameters parameter -6 speed grade -7 speed grade -8 speed grade unit minimum maximum minimum maximum minimum maximum t su 47 54 62 ps t h 110 111 113 ps t co 0 0 0 ps t inreg2pipe9 1379 1872 2441 ps t inreg2pipe18 1379 1872 2441 ps t pipe2outreg 104 142 185 ps t pd9 2470 3353 4370 ps t pd18 2903 3941 5136 ps t clr 2686 3129 3572 ps t clkl 1923 2307 2769 ps t clkh 1923 2307 2769 ps table 5?19. m4k block internal timing microparameters (part 1 of 2) parameter -6 speed grade -7 speed grade -8 speed grade unit minimum maximum minimum maximum minimum maximum t m4krc 3764 4248 4736 ps t m4kweresu 35 40 46 ps t m4kwereh 234 250 267 ps t m4kbesu 35 40 46 ps t m4kbeh 234 250 267 ps t m4kdataasu 35 40 46 ps t m4kdataah 234 250 267 ps t m4kaddrasu 35 40 46 ps t m4kaddrah 234 250 267 ps t m4kdatabsu 35 40 46 ps t m4kdatabh 234 250 267 ps t m4kraddrbsu 35 40 46 ps
5?20 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications cyclone ii clock timing parameters see tables 5?20 through 5?32 for cyclone ii clock timing parameters. ep2c5 clock timing parameters tables 5?21 and 5?22 show the clock timing parameters for ep2c5 devices t m4kraddrbh 234 250 267 ps t m4kdataco1 724 826 930 ps t m4kdataco2 3680 4157 4636 ps t m4kclkh 1923 2307 2769 ps t m4kclkl 1923 2307 2769 ps t m4kclr 191 217 244 ps table 5?19. m4k block internal timing microparameters (part 2 of 2) parameter -6 speed grade -7 speed grade -8 speed grade unit minimum maximum minimum maximum minimum maximum table 5?20. cyclone ii clock timing parameters symbol parameter t cin delay from clock pad to i/o input register t cout delay from clock pad to i/o output register t pllcin delay from pll inclk pad to i/o input register t pllcout delay from pll inclk pad to i/o output register table 5?21. ep2c5 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.307 2.462 2.663 ns t cout 2.344 2.497 2.696 ns t pllcin 0.339 0.324 0.361 ns t pllcout 0.376 0.359 0.394 ns
altera corporation 5?21 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ep2c 8 clock timing parameters tables 5?23 and 5?24 show the clock timing parameters for ep2c8 devices. table 5?22. ep2c5 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.185 2.326 2.515 ns t cout 2.204 2.342 2.527 ns t pllcin 0.217 0.189 0.213 ns t pllcout 0.236 0.205 0.225 ns table 5?23. ep2c8 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.394 2.554 2.762 ns t cout 2.431 2.589 2.795 ns t pllcin 0.389 0.377 0.417 ns t pllcout 0.426 0.412 0.45 ns table 5?24. ep2c8 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.253 2.401 2.595 ns t cout 2.272 2.417 2.607 ns t pllcin 0.248 0.224 0.25 ns t pllcout 0.267 0.24 0.262 ns
5?22 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications ep2c20 clock timing parameters tables 5?25 and 5?26 show the clock timing parameters for ep2c20 devices. ep2c35 clock timing parameters tables 5?27 and 5?28 show the clock timing parameters for ep2c35 devices. table 5?25. ep2c20 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.471 2.638 2.850 ns t cout 2.508 2.673 2.883 ns t pllcin 0.231 0.209 0.231 ns t pllcout 0.268 0.244 0.264 ns table 5?26. ep2c20 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.367 2.522 2.726 ns t cout 2.386 2.538 2.738 ns t pllcin 0.125 0.093 0.107 ns t pllcout 0.144 0.109 0.119 ns table 5?27. ep2c35 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.611 2.784 3.008 ns t cout 2.648 2.819 3.041 ns t pllcin 0.218 0.193 0.217 ns t pllcout 0.255 0.228 0.25 ns
altera corporation 5?23 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ep2c50 clock timing parameters tables 5?29 and 5?30 show the clock timing parameters for ep2c50 devices. table 5?28. ep2c35 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.480 2.641 2.852 ns t cout 2.499 2.657 2.864 ns t pllcin 0.087 0.05 0.061 ns t pllcout 0.106 0.066 0.073 ns table 5?29. ep2c50 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.743 2.924 3.158 ns t cout 2.780 2.959 3.191 ns t pllcin 0.269 0.246 0.273 ns t pllcout 0.306 0.281 0.306 ns table 5?30. ep2c50 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.577 2.745 2.963 ns t cout 2.596 2.761 2.975 ns t pllcin 0.103 0.067 0.078 ns t pllcout 0.122 0.083 0.09 ns
5?24 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications ep2c70 clock timing parameters tables 5?31 and 5?32 show the clock timing parameters for ep2c70 devices table 5?31. ep2c70 column pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.892 3.083 3.327 ns t cout 2.929 3.118 3.360 ns t pllcin 0.335 0.317 0.351 ns t pllcout 0.372 0.352 0.384 ns table 5?32. ep2c70 row pins global clock timing parameters parameter -6 speed grade -7 speed grade -8 speed grade unit t cin 2.695 2.869 3.094 ns t cout 2.714 2.885 3.106 ns t pllcin 0.138 0.103 0.118 ns t pllcout 0.157 0.119 0.13 ns
altera corporation 5?25 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications ioe programmable delay see tables 5?33 and 5?34 for ioe programmable delay. table 5?33. cyclone ii ioe programm able delay on column pins note (1) parameter paths affected number of settings -6 speed grade -7 speed grade -8 speed grade unit min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad i/o dataout to core 7 0 3827 0 4088 0 4349 ps input delay from pin to input register pad i/o input register 56 0 8382 0 8836 0 9289 ps delay from output register to output pin i/o output register pad 2 0 563 0 617 0 670 ps notes to table 5?33 : (1) the incremental values for the settings are generally linear. for exact values of each setting, please use the latest version of quartus ii software. table 5?34. cyclone ii ioe program mable delay on row pins note (1) parameter paths affected number of settings -6 speed grade -7 speed grade -8 speed grade unit min offset max offset min offset max offset min offset max offset input delay from pin to internal cells pad -> i/o dataout to core 7 0 3776 0 4033 0 4290 ps input delay from pin to input register pad -> i/o input register 56 0 8258 0 8704 0 9149 ps delay from output register to output pin i/o output register -> pad 2 0 572 0 626 0 682 ps notes to table 5?34 : (1) the incremental values for the settings are generally linear. for exact values of each setting, please use the latest version of quartus ii software.
5?26 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications default capacitive loading of different i/o standards see table 5?35 for default capacitive loading of different i/o standards. table 5?35. default loading of different i/o standards for cyclone ii i/o standard capacitive load unit lvttl 0 pf lv c m o s 0 p f 2.5 v 0 pf 1.8 v 0 pf 1.5 v 0 pf pci 10 pf pci-x 10 pf sstl-2 class i 0 pf sstl-2 class ii 0 pf sstl-18 class i 0 pf sstl-18 class ii 0 pf 1.5-v hstl class i 0 pf 1.5-v hstl class ii 0 pf 1.8-v hstl class i 0 pf 1.8-v hstl class ii 0 pf differential sstl-2 class i 0 pf differential sstl-2 class ii 0 pf differential sstl-18 class i 0 pf differential sstl-18 class ii 0 pf 1.5-v differential hstl class i 0 pf 1.5-v differential hstl class ii 0 pf 1.8-v differential hstl class i 0 pf 1.8-v differential hstl class ii 0 pf lv d s 0 p f
altera corporation 5?27 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications i/o delays see tables 5?36 through 5?40 for i/o delays. table 5?36. i/o delay parameters symbol parameter t dip delay from i/o datain to output pad t op delay from i/o output register to output pad t pcout delay from input pad to i/o dataout to core t pi delay from input pad to i/o input register table 5?37. cyclone ii i/o input dela y for column pins (part 1 of 2) i/o standard parameter -6 speed grade -7 speed grade -8 speed grade unit lvttl t pi 1409 1490 1619 ps t pcout 760 783 854 ps 2.5v t pi 1379 1500 1620 ps t pcout 730 793 855 ps 1.8v t pi 1559 1690 1821 ps t pcout 910 983 1056 ps 1.5v t pi 1626 1759 1893 ps t pcout 977 1052 1128 ps lvcmos t pi 1409 1490 1619 ps t pcout 760 783 854 ps sstl_2_class_i t pi 1177 1277 1377 ps t pcout 528 570 612 ps sstl_2_class_ii t pi 1177 1277 1377 ps t pcout 528 570 612 ps sstl_18_class_i t pi 1214 1297 1382 ps t pcout 565 590 617 ps sstl_18_class_ii t pi 1214 1297 1382 ps t pcout 565 590 617 ps
5?28 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications 1.5v_hstl_class_i t pi 1332 1438 1545 ps t pcout 683 731 780 ps 1.5v_hstl_class_ii t pi 1332 1438 1545 ps t pcout 683 731 780 ps 1.8v_hstl_class_i t pi 1214 1297 1382 ps t pcout 565 590 617 ps 1.8v_hstl_class_ii t pi 1214 1297 1382 ps t pcout 565 590 617 ps differential_sstl_2_class_i t pi 1177 1277 1377 ps t pcout 528 570 612 ps differential_sstl_2_class_ii t pi 1177 1277 1377 ps t pcout 528 570 612 ps differential_sstl_18_class_i t pi 1214 1297 1382 ps t pcout 565 590 617 ps differential_sstl_18_class_ii t pi 1214 1297 1382 ps t pcout 565 590 617 ps differential_hstl_18_class_i t pi 1214 1297 1382 ps t pcout 565 590 617 ps differential_hstl_18_class_ii t pi 1214 1297 1382 ps t pcout 565 590 617 ps differential_hstl_15_class_i t pi 1332 1438 1545 ps t pcout 683 731 780 ps differential_hstl_15_class_ii t pi 1332 1438 1545 ps t pcout 683 731 780 ps lvds t pi 1259 1337 1415 ps t pcout 610 630 650 ps table 5?37. cyclone ii i/o input dela y for column pins (part 2 of 2) i/o standard parameter -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?29 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?38. cyclone ii i/o input de lay for row pins (part 1 of 2) i/o standard parameter -6 speed grade -7 speed grade -8 speed grade unit lvttl t pi 1328 1460 1641 ps t pcout 762 784 855 ps 2.5v t pi 1298 1471 1645 ps t pcout 732 795 859 ps 1.8v t pi 1477 1660 1844 ps t pcout 911 984 1058 ps 1.5v t pi 1544 1729 1914 ps t pcout 978 1053 1128 ps lvcmos t pi 1328 1460 1641 ps t pcout 762 784 855 ps sstl_2_class_i t pi 1095 1247 1399 ps t pcout 529 571 613 ps sstl_2_class_ii t pi 1095 1247 1399 ps t pcout 529 571 613 ps sstl_18_class_i t pi 1132 1267 1405 ps t pcout 566 591 619 ps sstl_18_class_ii t pi 1132 1267 1405 ps t pcout 566 591 619 ps 1.5v_hstl_class_i t pi 1250 1409 1568 ps t pcout 684 733 782 ps 1.5v_hstl_class_ii t pi 1250 1409 1568 ps t pcout 684 733 782 ps 1.8v_hstl_class_i t pi 1132 1267 1405 ps t pcout 566 591 619 ps 1.8v_hstl_class_ii t pi 1132 1267 1405 ps t pcout 566 591 619 ps differential_sstl_2_class_i t pi 1095 1247 1399 ps t pcout 529 571 613 ps differential_sstl_2_class_ii t pi 1095 1247 1399 ps t pcout 529 571 613 ps
5?30 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications differential_sstl_18_class_i t pi 1132 1267 1405 ps t pcout 566 591 619 ps differential_sstl_18_class_ii t pi 1132 1267 1405 ps t pcout 566 591 619 ps differential_hstl_18_class_i t pi 1132 1267 1405 ps t pcout 566 591 619 ps differential_hstl_18_class_ii t pi 1132 1267 1405 ps t pcout 566 591 619 ps differential_hstl_15_class_i t pi 1250 1409 1568 ps t pcout 684 733 782 ps differential_hstl_15_class_ii t pi 1250 1409 1568 ps t pcout 684 733 782 ps lvds t pi 1235 1375 1514 ps t pcout 669 699 728 ps pci t pi 1312 1456 1633 ps t pcout 746 780 847 ps pci-x t pi 1312 1456 1633 ps t pcout 746 780 847 ps table 5?38. cyclone ii i/o input de lay for row pins (part 2 of 2) i/o standard parameter -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?31 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?39. cyclone ii i/o output dela y for column pins (part 1 of 5) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit lvttl 4ma t op 2903 3125 3348 ps t dip 3073 3319 3567 ps 8ma t op 2670 2866 3061 ps t dip 2840 3060 3280 ps 12ma t op 2547 2735 2924 ps t dip 2717 2929 3143 ps 16ma t op 2478 2665 2851 ps t dip 2648 2859 3070 ps 20ma t op 2456 2641 2827 ps t dip 2626 2835 3046 ps 24ma(1) t op 2452 2637 2822 ps t dip 2622 2831 3041 ps lvcmos 4ma t op 2509 2695 2880 ps t dip 2679 2889 3099 ps 8ma t op 2473 2660 2847 ps t dip 2643 2854 3066 ps 12ma t op 2428 2613 2797 ps t dip 2598 2807 3016 ps 16ma t op 2403 2587 2772 ps t dip 2573 2781 2991 ps 20ma t op 2378 2562 2745 ps t dip 2548 2756 2964 ps 24ma(1) t op 2382 2566 2749 ps t dip 2552 2760 2968 ps
5?32 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications 2.5v 4ma t op 2478 2614 2750 ps t dip 2648 2808 2969 ps 8ma t op 2307 2434 2561 ps t dip 2477 2628 2780 ps 12ma t op 2192 2314 2437 ps t dip 2362 2508 2656 ps 16ma(1) t op 2152 2263 2382 ps t dip 2322 2457 2601 ps 1.8v 2ma t op 3988 4279 4570 ps t dip 4158 4473 4789 ps 4ma t op 3301 3538 3775 ps t dip 3471 3732 3994 ps 6ma t op 2993 3195 3398 ps t dip 3163 3389 3617 ps 8ma t op 2882 3074 3266 ps t dip 3052 3268 3485 ps 10ma t op 2853 3041 3230 ps t dip 3023 3235 3449 ps 12ma(1) t op 2853 3041 3230 ps t dip 3023 3235 3449 ps 1.5v 2ma t op 4477 4870 5263 ps t dip 4647 5064 5482 ps 4ma t op 3649 3965 4281 ps t dip 3819 4159 4500 ps 6ma t op 3527 3823 4119 ps t dip 3697 4017 4338 ps 8ma(1) t op 3537 3827 4118 ps t dip 3707 4021 4337 ps sstl_2_class_i 8ma t op 2388 2516 2645 ps t dip 2558 2710 2864 ps 12ma(1) t op 2277 2401 2525 ps t dip 2447 2595 2744 ps table 5?39. cyclone ii i/o output dela y for column pins (part 2 of 5) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?33 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications sstl_2_class_ii 16ma t op 2245 2365 2486 ps t dip 2415 2559 2705 ps 20ma t op 2231 2351 2471 ps t dip 2401 2545 2690 ps 24ma(1) t op 2225 2345 2465 ps t dip 2395 2539 2684 ps sstl_18_class_i 6ma t op 3140 3345 3549 ps t dip 3310 3539 3768 ps 8ma t op 3086 3287 3489 ps t dip 3256 3481 3708 ps 10ma t op 2980 3171 3361 ps t dip 3150 3365 3580 ps 12ma(1) t op 2980 3171 3361 ps t dip 3150 3365 3580 ps sstl_18_class_ii 16ma t op 2905 3088 3270 ps t dip 3075 3282 3489 ps 18ma(1) t op 2900 3082 3264 ps t dip 3070 3276 3483 ps 1.8v_hstl_class_i 8ma t op 3222 3424 3625 ps t dip 3392 3618 3844 ps 10ma t op 3090 3279 3469 ps t dip 3260 3473 3688 ps 12ma(1) t op 3090 3279 3469 ps t dip 3260 3473 3688 ps 1.8v_hstl_class_ii 16ma t op 2936 3107 3278 ps t dip 3106 3301 3497 ps 18ma t op 2924 3101 3279 ps t dip 3094 3295 3498 ps 20ma(1) t op 2926 3096 3266 ps t dip 3096 3290 3485 ps table 5?39. cyclone ii i/o output dela y for column pins (part 3 of 5) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
5?34 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications 1.5v_hstl_class_i 8ma t op 4292 4637 4981 ps t dip 4462 4831 5200 ps 10ma t op 4031 4355 4680 ps t dip 4201 4549 4899 ps 12ma(1) t op 4031 4355 4680 ps t dip 4201 4549 4899 ps 1.5v_hstl_class_ii 16ma(1) t op 3844 4125 4406 ps t dip 4014 4319 4625 ps differential_sstl_2_ class_i 8ma t op 2388 2516 2645 ps t dip 2558 2710 2864 ps 12ma t op 2277 2401 2525 ps t dip 2447 2595 2744 ps differential_sstl_2_ class_ii 16ma t op 2245 2365 2486 ps t dip 2415 2559 2705 ps 20ma t op 2231 2351 2471 ps t dip 2401 2545 2690 ps 24ma t op 2225 2345 2465 ps t dip 2395 2539 2684 ps differential_sstl_18 _class_i 6ma t op 3140 3345 3549 ps t dip 3310 3539 3768 ps 8ma t op 3086 3287 3489 ps t dip 3256 3481 3708 ps 10ma t op 2980 3171 3361 ps t dip 3150 3365 3580 ps 12ma t op 2980 3171 3361 ps t dip 3150 3365 3580 ps differential_sstl_18 _class_ii 16ma t op 2905 3088 3270 ps t dip 3075 3282 3489 ps 18ma t op 2900 3082 3264 ps t dip 3070 3276 3483 ps table 5?39. cyclone ii i/o output dela y for column pins (part 4 of 5) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?35 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications differential_hstl_18 _class_i 8ma t op 3222 3424 3625 ps t dip 3392 3618 3844 ps 10ma t op 3090 3279 3469 ps t dip 3260 3473 3688 ps 12ma t op 3090 3279 3469 ps t dip 3260 3473 3688 ps differential_hstl_18 _class_ii 16ma t op 2936 3107 3278 ps t dip 3106 3301 3497 ps 18ma t op 2924 3101 3279 ps t dip 3094 3295 3498 ps 20ma t op 2926 3096 3266 ps t dip 3096 3290 3485 ps differential_hstl_15 _class_i 8ma t op 4292 4637 4981 ps t dip 4462 4831 5200 ps 10ma t op 4031 4355 4680 ps t dip 4201 4549 4899 ps 12ma t op 4031 4355 4680 ps t dip 4201 4549 4899 ps differential_hstl_15 _class_ii 16ma t op 3844 4125 4406 ps t dip 4014 4319 4625 ps lvds - t op 2243 2344 2445 ps t dip 2413 2538 2664 ps rsds - t op 2243 2344 2445 ps t dip 2413 2538 2664 ps mini_lvds - t op 2243 2344 2445 ps t dip 2413 2538 2664 ps note to table 5?39 : (1) this is the default setting in quartus ii software. table 5?39. cyclone ii i/o output dela y for column pins (part 5 of 5) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
5?36 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications table 5?40. cyclone ii i/o output de lay for row pins (part 1 of 4) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit lvttl 4ma t op 2539 2694 2891 ps t dip 2747 2931 3158 ps 8ma t op 2411 2587 2762 ps t dip 2619 2824 3029 ps 12ma t op 2282 2452 2620 ps t dip 2490 2689 2887 ps 16ma t op 2286 2455 2624 ps t dip 2494 2692 2891 ps 20ma t op 2245 2413 2580 ps t dip 2453 2650 2847 ps 24ma(1) t op 2253 2422 2589 ps t dip 2461 2659 2856 ps lvcmos 4ma t op 2231 2396 2561 ps t dip 2439 2633 2828 ps 8ma t op 2260 2429 2597 ps t dip 2468 2666 2864 ps 12ma(1) t op 2217 2383 2549 ps t dip 2425 2620 2816 ps 2.5v 4ma t op 2350 2477 2604 ps t dip 2558 2714 2871 ps 8ma(1) t op 2177 2296 2415 ps t dip 2385 2533 2682 ps
altera corporation 5?37 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications 1.8v 2ma t op 3657 3927 4196 ps t dip 3865 4164 4463 ps 4ma t op 3010 3226 3440 ps t dip 3218 3463 3707 ps 6ma t op 2857 3050 3242 ps t dip 3065 3287 3509 ps 8ma t op 2714 2897 3078 ps t dip 2922 3134 3345 ps 10ma t op 2714 2897 3078 ps t dip 2922 3134 3345 ps 12ma(1) t op 2678 2856 3034 ps t dip 2886 3093 3301 ps 1.5v 2ma t op 4127 4492 4855 ps t dip 4335 4729 5122 ps 4ma t op 3452 3747 4042 ps t dip 3660 3984 4309 ps 6ma(1) t op 3452 3747 4042 ps t dip 3660 3984 4309 ps sstl_2_class_i 8ma t op 2152 2268 2382 ps t dip 2360 2505 2649 ps 12ma(1) t op 2131 2246 2360 ps t dip 2339 2483 2627 ps sstl_2_class_ii 16ma(1) t op 2067 2177 2287 ps t dip 2275 2414 2554 ps sstl_18_class_i 6ma t op 2828 3018 3206 ps t dip 3036 3255 3473 ps 8ma t op 2832 3024 3215 ps t dip 3040 3261 3482 ps 10ma(1) t op 2806 2990 3173 ps t dip 3014 3227 3440 ps table 5?40. cyclone ii i/o output de lay for row pins (part 2 of 4) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
5?38 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications 1.8v_hstl_class_i 8ma t op 2853 3017 3184 ps t dip 3061 3254 3451 ps 10ma t op 2842 3011 3179 ps t dip 3050 3248 3446 ps 12ma(1) t op 2842 3011 3179 ps t dip 3050 3248 3446 ps 1.5v_hstl_class_i 8ma(1) t op 3642 3917 4191 ps t dip 3850 4154 4458 ps differential_sstl_2_ class_i 8ma t op 2152 2268 2382 ps t dip 2360 2505 2649 ps 12ma t op 2131 2246 2360 ps t dip 2339 2483 2627 ps differential_sstl_2_ class_ii 16ma t op 2067 2177 2287 ps t dip 2275 2414 2554 ps differential_sstl_18 _class_i 6ma t op 2828 3018 3206 ps t dip 3036 3255 3473 ps 8ma t op 2832 3024 3215 ps t dip 3040 3261 3482 ps 10ma t op 2806 2990 3173 ps t dip 3014 3227 3440 ps differential_hstl_18 _class_i 8ma t op 2853 3017 3184 ps t dip 3061 3254 3451 ps 10ma t op 2842 3011 3179 ps t dip 3050 3248 3446 ps 12ma t op 2842 3011 3179 ps t dip 3050 3248 3446 ps differential_hstl_15 _class_i 8ma t op 3642 3917 4191 ps t dip 3850 4154 4458 ps lvds - t op 2089 2184 2278 ps t dip 2297 2421 2545 ps rsds - t op 2089 2184 2278 ps t dip 2297 2421 2545 ps table 5?40. cyclone ii i/o output de lay for row pins (part 3 of 4) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?39 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications maximum input & output clock rate tables 5?41 through 5?44 show the i/o toggle rates for cyclone ii devices. mini_lvds - t op 2089 2184 2278 ps t dip 2297 2421 2545 ps pci - t op 2070 2214 2358 ps t dip 2278 2451 2625 ps pci_x - t op 2070 2214 2358 ps t dip 2278 2451 2625 ps notes to table 5?45 : (1) this is the default setting in quartus ii software. table 5?40. cyclone ii i/o output de lay for row pins (part 4 of 4) i/o standard drive strength parameter -6 speed grade -7 speed grade -8 speed grade unit table 5?41. cyclone ii maximum input clock rate for column pins (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 450 405 360 mhz 2.5v 450 405 360 mhz 1.8v 450 405 360 mhz 1.5v 300 270 240 mhz lvcmos 450 405 360 mhz sstl_2_class_i 500 500 500 mhz sstl_2_class_ii 500 500 500 mhz sstl_18_class_i 500 500 500 mhz sstl_18_class_ii 500 500 500 mhz 1.5v_hstl_class_i 500 500 500 mhz 1.5v_hstl_class_ii 500 500 500 mhz 1.8v_hstl_class_i 500 500 500 mhz 1.8v_hstl_class_ii 500 500 500 mhz differential_sstl_2_class_i 500 500 500 mhz differential_sstl_2_class_ii 500 500 500 mhz differential_sstl_18_class_i 500 500 500 mhz differential_sstl_18_class_ii 500 500 500 mhz
5?40 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications differential_hstl_18_class_i 500 500 500 mhz differential_hstl_18_class_ii 500 500 500 mhz differential_hstl_15_class_i 500 500 500 mhz differential_hstl_15_class_ii 500 500 500 mhz lvds 402 402 402 mhz table 5?41. cyclone ii maximum input clock rate for column pins (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit table 5?42. cyclone ii maximum input clock rate for row pins i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 450 405 360 mhz 2.5v 450 405 360 mhz 1.8v 450 405 360 mhz 1.5v 300 270 240 mhz lvcmos 450 405 360 mhz sstl_2_class_i 500 500 500 mhz sstl_2_class_ii 500 500 500 mhz sstl_18_class_i 500 500 500 mhz sstl_18_class_ii 500 500 500 mhz 1.5v_hstl_class_i 500 500 500 mhz 1.5v_hstl_class_ii 500 500 500 mhz 1.8v_hstl_class_i 500 500 500 mhz 1.8v_hstl_class_ii 500 500 500 mhz differential_sstl_2_class_i 500 500 500 mhz differential_sstl_2_class_ii 500 500 500 mhz differential_sstl_18_class_i 500 500 500 mhz differential_sstl_18_class_ii 500 500 500 mhz differential_hstl_18_class_i 500 500 500 mhz differential_hstl_18_class_ii 500 500 500 mhz differential_hstl_15_class_i 500 500 500 mhz differential_hstl_15_class_ii 500 500 500 mhz lvds 402 402 402 mhz pci 350 315 280 mhz pci-x 350 315 280 mhz
altera corporation 5?41 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications table 5?43. cyclone ii maximum output clock rate for column pins i/o standard drive strength -6 speed grade -7 speed grade -8 speed grade unit lvttl 4ma 120 100 80 mhz 8ma 200 170 140 mhz 12ma 280 230 190 mhz 16ma 290 240 200 mhz 20ma 330 280 230 mhz 24ma (1) 360 300 250 mhz lvcmos 4ma 250 210 170 mhz 8ma 280 230 190 mhz 12ma 310 260 210 mhz 16ma 320 270 220 mhz 20ma 350 290 240 mhz 24ma (1) 370 310 250 mhz 2.5v 4ma 180 150 120 mhz 8ma 280 230 190 mhz 12ma 440 370 300 mhz 16ma (1) 450 405 350 mhz 1.8v 2ma 120 100 80 mhz 4ma 180 150 120 mhz 6ma 220 180 150 mhz 8ma 240 200 160 mhz 10ma 300 250 210 mhz 12ma (1) 350 290 240 mhz 1.5v 2ma 80 60 50 mhz 4ma 130 110 90 mhz 6ma 180 150 120 mhz 8ma (1) 230 190 160 mhz sstl_2_class_i 8ma 400 340 280 mhz 12ma (1) 400 340 280 mhz sstl_2_class_ii 16ma 350 290 240 mhz 20ma 400 340 280 mhz 24ma (1) 400 340 280 mhz
5?42 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications sstl_18_class_i 6ma 260 220 180 mhz 8ma 260 220 180 mhz 10ma 270 220 180 mhz 12ma (1) 280 230 190 mhz sstl_18_class_ii 16ma 260 220 180 mhz 18ma (1) 270 220 180 mhz 1.8v_hstl_class_i 8ma 260 220 180 mhz 10ma 300 250 210 mhz 12ma (1) 320 270 220 mhz 1.8v_hstl_class_ii 16ma 230 190 160 mhz 18ma 240 200 160 mhz 20ma (1) 250 210 170 mhz 1.5v_hstl_class_i 8ma 210 170 140 mhz 10ma 220 180 150 mhz 12ma (1) 230 190 160 mhz 1.5v_hstl_class_ii 16ma (1) 210 170 140 mhz differential_sstl_2_ class_i 8ma 400 340 280 mhz 12ma 400 340 280 mhz differential_sstl_2_ class_ii 16ma 350 290 240 mhz 20ma 400 340 280 mhz 24ma 400 340 280 mhz differential_sstl_18 _class_i 6ma 260 220 180 mhz 8ma 260 220 180 mhz 10ma 270 220 180 mhz 12ma 280 230 190 mhz differential_sstl_18 _class_ii 16ma 260 220 180 mhz 18ma 270 220 180 mhz differential_hstl_18 _class_i 8ma 260 220 180 mhz 10ma 300 250 210 mhz 12ma 320 270 220 mhz differential_hstl_18 _class_ii 16ma 230 190 160 mhz 18ma 240 200 160 mhz 20ma 250 210 170 mhz table 5?43. cyclone ii maximum output clock rate for column pins i/o standard drive strength -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?43 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications differential_hstl_15 _class_i 8ma 210 170 140 mhz 10ma 220 180 150 mhz 12ma 230 190 160 mhz differential_hstl_15 _class_ii 16ma 210 170 140 mhz lvds - 400 340 280 mhz rsds - 400 340 280 mhz mini_lvds - 400 340 280 mhz note to table 5?43 : (1) this is the default setting in quartus ii software. table 5?43. cyclone ii maximum output clock rate for column pins i/o standard drive strength -6 speed grade -7 speed grade -8 speed grade unit table 5?44. cyclone ii maximum out put clock rate for row pins i/o standard drive strength -6 speed grade -7 speed grade -8 speed grade unit lvttl 4ma 120 100 80 mhz 8ma 200 170 140 mhz 12ma 280 230 190 mhz 16ma 290 240 200 mhz 20ma 330 280 230 mhz 24ma (1) 360 300 250 mhz lvcmos 4ma 250 210 170 mhz 8ma 280 230 190 mhz 12ma (1) 310 260 210 mhz 2.5v 4ma 180 150 120 mhz 8ma (1) 280 230 190 mhz 1.8v 2ma 120 100 80 mhz 4ma 180 150 120 mhz 6ma 220 180 150 mhz 8ma 240 200 160 mhz 10ma 300 250 210 mhz 12ma (1) 350 290 240 mhz
5?44 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications 1.5v 2ma 80 60 50 mhz 4ma 130 110 90 mhz 6ma (1) 180 150 120 mhz sstl_2_class_i 8ma 400 340 280 mhz 12ma (1) 400 340 280 mhz sstl_2_class_ii 16ma (1) 350 290 240 mhz sstl_18_class_i 6ma 260 220 180 mhz 8ma 260 220 180 mhz 10ma (1) 270 220 180 mhz hstl_18_class_i 8ma 260 220 180 mhz 10ma 300 250 210 mhz 12ma (1) 320 270 220 mhz hstl_15_class_i 8ma (1) 210 170 140 mhz differential_sstl_2_ class_i 8ma 400 340 280 mhz 12ma 400 340 280 mhz differential_sstl_2_ class_ii 16ma 350 290 240 mhz differential_sstl_18 _class_i 6ma 260 220 180 mhz 8ma 260 220 180 mhz 10ma 270 220 180 mhz differential_hstl_18 _class_i 8ma 260 220 180 mhz 10ma 300 250 210 mhz 12ma 320 270 220 mhz differential_hstl_15 _class_i 8ma 210 170 140 mhz lvds - 400 340 280 mhz rsds - 400 340 280 mhz mini_lvds - 400 340 280 mhz pci - 350 315 280 mhz pci_x - 350 315 280 mhz note to table 5?44 : (1) this is the default setting in quartus ii software. table 5?44. cyclone ii maximum out put clock rate for row pins i/o standard drive strength -6 speed grade -7 speed grade -8 speed grade unit
altera corporation 5?45 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications high speed i/o timing specifications the timing analysis for lvds, mi ni-lvds, and rsds is different compared to other i/o standards because the data communication is source-synchronous. you should also consider board skew, cable skew, and clock jitter in your calculation. this section provides details on the timing parameters for high-speed i/o standards in cyclone ii devices. table 5?45 defines the parameters of the timing diagram shown in figure 5?3 . table 5?45. high-speed i/o timing definitions parameter symbol description high-speed clock f hscklk high-speed receiver and transmitte r input and output clock frequency. duty cycle t duty duty cycle on high-speed transmitter output clock. high-speed i/o data rate hsiodr high-speed receiv er and transmitter input and output data rate. time unit interval tui tui = 1/hsiodr. channel-to-channel skew tccs the ti ming difference between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. tccs = tui ? sw ? (2 rskm) sampling window sw the period of time during wh ich the data must be valid in order for you to capture it correctly. sampling window is the sum of the setup time, hold time, and jitter. the window of t su + t h is expected to be centered in the sampling window. sw = tui ? tccs ? (2 rskm) receiver input skew margin rskm rskm is defined by the total margin left after accounting for the sampling window and tccs. rskm = (tui ? sw ? tccs) / 2 input jitter (peak to peak) peak-to-pea k input jitter on high-speed plls. output jitter (peak to peak) peak-t o-peak output jitter on high-speed plls. signal rise time t rise low-to-high transmission time. signal fall time t fall high-to-low transmission time. lock time t lock lock time for high-speed trans mitter and receiver plls.
5?46 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications figure 5?3. high-speed i/o timing diagram figure 5?4 shows the high-speed i/o timing budget. figure 5?4. high-speed i/o timing budget note (1) note to figure 5?4 : (1) the equation for the high-speed i/o timing budget is: period = tccs + rskm + sw + rskm. table 5?46 shows the rsds timing budg et for cyclone ii devices at 311 mbps. rsds is supported for tran smitting from cyclone ii devices. cyclone ii devices cannot receive rsds data because the devices are intended for applications where they will be driving display drivers. sampling window (sw) time unit interval (tui) rskm tccs rskm tccs internal clock external input clock receiver input data internal clock period rskm 0.5 tccs rskm 0.5 tccs sw
altera corporation 5?47 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications cyclone ii devices support a maximum rs ds data rate of 311 mbps using ddio registers. cyclone ii devices support rsds only in the commercial temperature range. in order to determine the transmitter timing requirements, rsds receiver timing requirements on the other end of the link must be taken into consideration. rsds receiver timing parameters are typically defined as table 5?46. rsds transmitte r timing specification symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) min typ max (1) min typ max (1) f hsclk (input clock frequency) 10 10 155.5 10 155.5 10 155.5 mhz 8 10 155.5 10 155.5 10 155.5 mhz 7 10 155.5 10 155.5 10 155.5 mhz 4 10 155.5 10 155.5 10 155.5 mhz 2 10 155.5 10 155.5 10 155.5 mhz 1 10 311 10 311 10 311 mhz device operation in mbps 10 100 311 100 311 100 311 mbps 8 80 311 80 311 80 311 mbps 7 70 311 70 311 70 311 mbps 4 40 311 40 311 40 311 mbps 2 20 311 20 311 20 311 mbps 1 10 311 10 311 10 311 mbps t duty 45 55 45 55 45 55 % tccs 200 200 200 ps output jitter (peak to peak) 500 500 500 ps t rise 20?80%, c load = 5 pf 500 500 500 ps t fall 80?20%, c load = 5 pf 500 500 500 ps t lock 100 100 100 s note to table 5?46 : (1) these specifications are for a thre e-resistor rsds implementation. for si ngle-resistor rsds in 10 through 2 modes, the maximum data rate is 170 mbps and the co rresponding maximum input clock frequency is 85 mhz. for single-resistor rsds in 1 mode, the maximum data rate is 170 mbps and the maximum input clock frequency is 170 mhz. see chapter 11 for more inform ation on the different rsds implementations.
5?48 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications t su and t h requirements. therefore, the transmitter timing parameter specifications are t co (minimum) and t co (maximum). refer to figure 5?4 for the timing budget. the ac timing requirements for rsds are shown in figure 5?5 . figure 5?5. rsds transmitter cl ock to data relationship table 5?47 shows the mini-lvds transmitte r timing budget for cyclone ii devices at 311 mbps. cyclone ii devices can not receive mini-lvds data because the devices are intended for applications where they will be driving display drivers. a maximum mini-lvds data rate of 311 mbps is supported for cyclone ii devices using ddio registers. cyclone ii devices support mini-lvds only in the commercial temperature range. transmitter valid data transmitter valid data valid data total skew valid data t su (2 ns) t h (2 ns) channel-to-channel skew (1.68 ns) transmitter clock (5.88 ns) at transmitter tx_data[11..0] at receiver rx_data[11..0] table 5?47. mini-lvds transmitter ti ming specification (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 10 155.5 10 155.5 10 155.5 mhz 8 10 155.5 10 155.5 10 155.5 mhz 7 10 155.5 10 155.5 10 155.5 mhz 4 10 155.5 10 155.5 10 155.5 mhz 2 10 155.5 10 155.5 10 155.5 mhz 1 10 311 10 311 10 311 mhz
altera corporation 5?49 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications in order to determine the transmitte r timing requirements, mini-lvds receiver timing requirements on th e other end of the link must be taken into consideration. mini -lvds receiver timing parameters are typically defined as t su and t h requirements. therefore, the transmitter timing parameter specifications are t co (minimum) and t co (maximum). refer to figure 5?4 for the timing budget. the ac timing requirements for mini-lvds are shown in figure 5?6 . figure 5?6. mini-lvds transmitte r ac timing specification notes to figure 5?6 : (1) the data setup time, t su , is 0.225 tui. (2) the data hold time, t h , is 0.225 tui. device operation in mbps 10 100 311 100 311 100 311 mbps 8 80 311 80 311 80 311 mbps 7 70 311 70 311 70 311 mbps 4 40 311 40 311 40 311 mbps 2 20 311 20 311 20 311 mbps 1 10 311 10 311 10 311 mbps t duty 45 55 45 55 45 55 % tccs 200 200 200 ps output jitter (peak to peak) 500 500 500 ps t rise 20?80% 500 500 500 ps t fall 80?20% 500 500 500 ps t lock 100 100 100 s table 5?47. mini-lvds transmitter ti ming specification (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max t su (1) t h (2) tui t su (1) t h (2) lvdsclk[]n lvdsclk[]p lvds[]p lvds[]n
5?50 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications tables 5?48 and 5?49 show the lvds timing budget for cyclone ii devices. cyclone ii devices support lv ds receivers at data rates up to 805 mbps and lvds transmitters at data rates up to 640 mbps. table 5?48. lvds transmitter ti ming specification (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) max (2) min typ max (1) max (2) min typ max (1) max (2) f hsclk (input clock fre- quency) 10 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 8 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 7 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 4 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 2 10 320 320 10 275 320 10 155.5 (4) 320 (6) mhz 1 10 402.5 402.5 10 402.5 402.5 10 402.5 ( 8 ) 402.5 ( 8 ) mhz hsiodr 10 100 640 640 100 550 640 100 311 (5) 550 (7) mbps 8 80 640 640 80 550 640 80 311 (5) 550 (7) mbps 7 70 640 640 70 550 640 70 311 (5) 550 (7) mbps 4 40 640 640 40 550 640 40 311 (5) 550 (7) mbps 2 20 640 640 20 550 640 20 311 (5) 550 (7) mbps 1 10 402.5 402.5 10 402.5 402.5 10 402.5 (9) 402.5 (9) mbps t duty 45 55 45 55 45 55 % 160 312.5 363.6 ps tccs (3) 200 200 200 ps output jitter (peak to peak) 500 500 550 (10) ps t rise 20?80% 150 200 250 150 200 250 150 200 250 (11) ps
altera corporation 5?51 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications t fall 80?20% 150 200 250 150 200 250 150 200 250 (11) ps t lock 100 100 100 (12) s notes to table 5?48 : (1) the maximum data rate that complies with duty cycle distortion of 45?55%. (2) the maximum data rate when taking duty cycle in abso lute ps into consideration that may not comply with 45?55% duty cycle distortion. if the downstream receiver can handle duty cycle distortion beyond the 45?55% range, you may use the higher data rate values from this column.you can calculate the duty cycle distortion as a percentage using the absolute ps value. for example, for a data rate of 640 mbps (ui = 1625 ps) and a t duty of 250 ps, the duty cycle distortion is t duty /(ui*2) *100% = 250 ps/(1625 *2) * 100% = 7.7%, which gives you a duty cycle distortion of 42.3-57.7%. (3) the tccs specification applies to the entire bank of lvds as long as the serdes logic is placed within the lab adjacent to the output pins. (4) for extended temperature devices, the maximum input clock frequency for 10 through 2 modes is 137.5 mhz. (5) for extended temperature device s, the maximum data rate for 10 through 2 modes is 275 mbps. (6) for extended temperatur e devices, the maximum input clock frequency for 10 through 2 modes is 200 mhz. (7) for extended temperature device s, the maximum data rate for 10 through 2 modes is 400 mbps. (8) for extended temperature devi ces, the maximum input clock frequency for 1 mode is 340 mhz. (9) for extended temperature de vices, the maximum data rate for 1 mode is 340 mbps. (10) for extended temperature de vices, the maximum output jitter (peak to peak) is 600 ps. (11) for extended temperature devices, the maximum t rise and t fall are 300 ps. (12) for extended temperat ure devices, the maximum lock time is 500 us. table 5?48. lvds transmitter ti ming specification (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max (1) max (2) min typ max (1) max (2) min typ max (1) max (2)
5?52 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications table 5?49. lvds receiver timing specification symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (input clock frequency) 10 10 402.5 10 320 10 320 (1) mhz 8 10 402.5 10 320 10 320 (1) mhz 7 10 402.5 10 320 10 320 (1) mhz 4 10 402.5 10 320 10 320 (1) mhz 2 10 402.5 10 320 10 320 (1) mhz 1 10 402.5 10 402.5 10 402.5 (3) mhz hsiodr 10 100 805 100 640 100 640 (2) mbps 8 80 805 80 640 80 640 (2) mbps 7 70 805 70 640 70 640 (2) mbps 4 40 805 40 640 40 640 (2) mbps 2 20 805 20 640 20 640 (2) mbps 1 10 402.5 10 402.5 10 402.5 (4) mbps sw 300 400 400 ps input jitter tolerance 500 500 550 ps t lock 100 100 100 (5) ps notes to table 5?49 : (1) for extended temperatur e devices, the maximum input clock frequency for x10 through x2 modes is 275 mhz. (2) for extended temperature device s, the maximum data rate for x10 through x2 modes is 550 mbps. (3) for extended temperature devi ces, the maximum input clock frequency for x1 mode is 340 mhz. (4) for extended temperature de vices, the maximum data rate for x1 mode is 340 mbps. (5) for extended temperat ure devices, the maximum lock time is 500 us.
altera corporation 5?53 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications jtag timing specifications figure 5?7 shows the timing requirements for the jtag signals. figure 5?7. cyclone ii jtag waveform tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
5?54 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications table 5?50 shows the jtag timing parameters and values for cyclone ii devices. 1 cyclone ii devices must be within the first 17 devices in a jtag chain. all of these devices have the same jtag controller. if any of the cyclone ii devices are in the 18th or after they will fail configuration. this does not affect the signaltap ? ii logic analyzer. f for more information on jtag, see the ieee 1149.1 (jtag) boundary-scan testing for cyclone ii devices chapter in the cyclone ii handbook and jam programming & test language specification . table 5?50. cyclone ii jtag timing parameters & values symbol parameter min max unit t jcp tck clock period 40 ns t jch tck clock high time 20 ns t jcl tck clock low time 20 ns t jpsu jtag port setup time (2) 5ns t jph jtag port hold time 10 ns t jpco jtag port clock to output (2) 13 ns t jpzx jtag port high impedance to valid output (2) 13 ns t jpxz jtag port valid output to high impedance (2) 13 ns t jssu capture register setup time (2) 5ns t jsh capture register hold time 10 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns notes to table 5?50 : (1) this information is preliminary. (2) this specification is shown for 3.3-v lvttl/lvcmos an d 2.5-v lvttl/lvcmos operation of the jtag pins. for 1.8-v lvttl/lvcmos and 1.5- v lvcmos, the jtag port and capture regi ster clock setup time is 3 ns and port clock to output time is 15 ns.
altera corporation 5?55 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications pll timing specifications table 5?51 describes the cyclone ii pll specifications when operating in both the commercial junction temper ature range (0 to 85 c) and the industrial junction temperature ra nge (-40 to 100 c). follow the pll specifications for ?8 spee d grade devices when operating in the industrial temperature range. table 5?51. pll specifications (part 1 of 2) note (1) symbol parameter min typ max unit f in input clock frequency (-6 speed grade) 10 (4) mhz input clock frequency (-7 speed grade) 10 (4) mhz input clock frequency (-8 speed grade) 10 (4) mhz f inpfd pfd input frequency (-6 speed grade) 10 402.5 mhz pfd input frequency (-7 speed grade) 10 402.5 mhz pfd input frequency (-8 speed grade) 10 402.5 mhz f induty input clock duty cycle 40 60 % t injitter (5) input clock period jitter 200 ps f out_ext (external clock output) pll output frequency (-6 speed grade) 10 (4) mhz pll output frequency (-7 speed grade) 10 (4) mhz pll output frequency (-8 speed grade) 10 (4) mhz f out (to global clock) pll output frequency (-6 speed grade) 10 402.5 mhz pll output frequency (-7 speed grade) 10 402.5 mhz pll output frequency (-8 speed grade) 10 402.5 mhz t outduty duty cycle for external clock output (when set to 50%) 45 55 % t jitter (p-p) (2) period jitter for external clock output f out_ext > 100 mhz 300 ps f out_ext 100 mhz 30 mui t lock time required to lock from end of device configuration 100 (6) s
5?56 altera corporation cyclone ii device handbook, volume 1 march 2006 timing specifications f vco (3) pll internal vco operating range 300 1,000 mhz t areset minimum pulse width on areset signal. 10 ns notes to table 5?51 : (1) these numbers are preliminary an d pending silicon characterization. (2) the t jitter specification for the pll[4..1]_out pins are dependent on the i/o pins in its vccio bank, how many of them are switching outputs, how much they toggle, an d whether or not they use programmable current strength. (3) if the design enables divide by 2, a 300- to 500-mhz internal vco frequency is available. (4) this parameter is limited in quartus ii software by the i/o maximum frequency. the maximum i/o frequency is different for each i/o standard. (5) cyclone ii plls can track a spread-spectrum input clock that has an input jitter within 200 ps. (6) for extended temperat ure devices, the maximum lock time is 500 us. table 5?51. pll specifications (part 2 of 2) note (1) symbol parameter min typ max unit
altera corporation 5?57 march 2006 cyclone ii device handbook, volume 1 dc characteristics & timing specifications
altera corporation 6?1 november 2005 preliminary 6. reference & ordering information software cyclone tm ii devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced ti ming analysis, signaltap ? ii logic analyzer, and device configuration. see the quartus ii handbook for more information on the quartus ii software features. the free quartus ii web edit ion software, available at www.altera.com , supports microsoft window s xp and windows 2000. the full version of quartus ii software is available thro ugh the altera subscription program. the full version of quartus ii software supports all altera devices, is available for windows xp, windows 2000, sun solaris, and red hat linux operating systems, and includes a free suite of popular ip megacore ? functions for dsp applications and interfacing to external memory devices. quartus ii soft ware and quartus ii web edition software support seamless integration with your favorite third party eda tools. device pin-outs device pin-outs for cyclone ii devices are available on the altera web site ( www.altera.com ). for more information co ntact altera applications. ordering information figure 6?1 describes the ordering codes for cyclone ii devices. for more information on a specific packag e, contact altera applications. cii51006-1.2
6?2 altera corporation cyclone ii device handbook, volume 1 november 2005 ordering information figure 6?1. cyclone ii device pa ckaging ordering information device type package type 6, 7, or 8, with 6 being the fastest number of pins for a particular package es: t: q: f: thin quad flat pack (tqfp) plastic quad flat pack (pqfp) fineline bga ep2c: cyclone ii 5 8 20 35 50 70 c: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count engineering sample 7 ep2c 70 c 324 fes indicates specific device options or shipment method. n: lead-free devices i:

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